| Commit message (Expand) | Author | Age | Files | Lines |
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| * | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-11-19 | 1 | -0/+522 |
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| | * | xilinx: Add simulation models for MULT18X18* and DSP48A*. | Marcin Kościelnicki | 2019-11-19 | 1 | -0/+511 |
| | * | xilinx: Add simulation model for IBUFG. | Marcin Kościelnicki | 2019-10-10 | 1 | -0/+11 |
| * | | Do not require changes to cells_sim.v; try and work out comb model | Eddie Hung | 2019-10-05 | 1 | -208/+16 |
| * | | Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dff | Eddie Hung | 2019-10-04 | 1 | -47/+47 |
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| | * | Rename abc_* names/attributes to more precisely be abc9_* | Eddie Hung | 2019-10-04 | 1 | -19/+19 |
| * | | More fixes | Eddie Hung | 2019-10-01 | 1 | -16/+16 |
| * | | Escape Verilog identifiers for legality outside of Yosys | Eddie Hung | 2019-10-01 | 1 | -48/+48 |
| * | | Remove need for $currQ port connection | Eddie Hung | 2019-09-30 | 1 | -80/+80 |
| * | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-09-30 | 1 | -0/+44 |
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| | * | Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py} | Eddie Hung | 2019-09-30 | 1 | -0/+44 |
| * | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-09-29 | 1 | -0/+463 |
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| | * | Merge remote-tracking branch 'origin/clifford/fix1381' into xc7dsp | Eddie Hung | 2019-09-19 | 1 | -8/+44 |
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| | * | | Mis-spell | Eddie Hung | 2019-09-18 | 1 | -10/+25 |
| | * | | Add pattern detection support for DSP48E1 model, check against vendor | Eddie Hung | 2019-09-18 | 1 | -4/+43 |
| | * | | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-09-05 | 1 | -26/+70 |
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| | * \ \ | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp | Eddie Hung | 2019-08-30 | 1 | -24/+79 |
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| | | * \ \ | Merge branch 'master' into xc7dsp | David Shah | 2019-08-30 | 1 | -24/+91 |
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| | * | \ \ \ | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-08-20 | 1 | -8/+20 |
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| | * | | | | | | Add assign PCOUT = P to DSP48E1 | Eddie Hung | 2019-08-13 | 1 | -0/+2 |
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| | * | | | | | Fix copy-pasta typo | Eddie Hung | 2019-08-08 | 1 | -2/+2 |
| | * | | | | | DSP48E1 sim model: add SIMD tests | David Shah | 2019-08-08 | 1 | -1/+1 |
| | * | | | | | DSP48E1 model: test CE inputs | David Shah | 2019-08-08 | 1 | -5/+8 |
| | * | | | | | DSP48E1 sim model: seq test working | David Shah | 2019-08-08 | 1 | -6/+13 |
| | * | | | | | DSP48E1 sim model: Comb, no pre-adder, mode working | David Shah | 2019-08-08 | 1 | -2/+3 |
| | * | | | | | [wip] sim model testing | David Shah | 2019-08-08 | 1 | -2/+2 |
| | * | | | | | [wip] sim model testing | David Shah | 2019-08-08 | 1 | -40/+49 |
| | * | | | | | [wip] DSP48E1 sim model improvements | David Shah | 2019-08-07 | 1 | -6/+82 |
| | * | | | | | [wip] DSP48E1 sim model improvements | David Shah | 2019-08-06 | 1 | -23/+120 |
| | * | | | | | [wip] DSP48E1 sim model improvements | David Shah | 2019-08-06 | 1 | -8/+75 |
| | * | | | | | Signedness | Eddie Hung | 2019-07-16 | 1 | -7/+7 |
| | * | | | | | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp | Eddie Hung | 2019-07-16 | 1 | -1/+1 |
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| | | * | | | | | xilinx: Add correct signed behaviour to DSP48E1 model | David Shah | 2019-07-16 | 1 | -1/+1 |
| | * | | | | | | Add support for {A,B,P}REG in DSP48E1 | Eddie Hung | 2019-07-16 | 1 | -5/+21 |
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| | * | | | | | Move DSP48E1 model out of cells_xtra, initial multiply one in cells_sim | Eddie Hung | 2019-07-15 | 1 | -0/+131 |
| * | | | | | | FDCE_1 does not have IS_CLR_INVERTED | Eddie Hung | 2019-09-29 | 1 | -1/+1 |
| * | | | | | | Big rework; flop info now mostly in cells_sim.v | Eddie Hung | 2019-09-28 | 1 | -47/+247 |
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| * | | | | | Use extractinv for synth_xilinx -ise | Marcin Kościelnicki | 2019-09-19 | 1 | -8/+44 |
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| * | | | | Remove trailing space | Eddie Hung | 2019-08-30 | 1 | -2/+2 |
| * | | | | Merge remote-tracking branch 'origin/master' into xaig_arrival | Eddie Hung | 2019-08-28 | 1 | -15/+78 |
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| | * | | | Add (* clkbuf_sink *) to SRLC16E, reorder ports to match vendor | Eddie Hung | 2019-08-28 | 1 | -3/+8 |
| | * | | | xilinx: Add SRLC16E primitive. | Marcin Kościelnicki | 2019-08-27 | 1 | -1/+21 |
| | * | | | Merge branch 'master' into mwk/xilinx_bufgmap | Eddie Hung | 2019-08-23 | 1 | -1/+1 |
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| | * \ \ \ | Merge branch 'master' into mwk/xilinx_bufgmap | Eddie Hung | 2019-08-23 | 1 | -11/+22 |
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| | * \ \ \ \ | Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap | Eddie Hung | 2019-08-23 | 1 | -14/+20 |
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| | * | | | | | move attributes to wires | Marcin Kościelnicki | 2019-08-13 | 1 | -33/+42 |
| | * | | | | | Add clock buffer insertion pass, improve iopadmap. | Marcin Kościelnicki | 2019-08-13 | 1 | -0/+16 |
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| * | | | | | Put attributes above port | Eddie Hung | 2019-08-23 | 1 | -19/+46 |
| * | | | | | Merge remote-tracking branch 'origin/master' into xaig_arrival | Eddie Hung | 2019-08-23 | 1 | -5/+10 |
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| | * | | | | Forgot one | Eddie Hung | 2019-08-23 | 1 | -1/+2 |
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