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| author | David Shah <dave@ds0.me> | 2019-08-08 10:05:11 +0100 |
|---|---|---|
| committer | David Shah <dave@ds0.me> | 2019-08-08 10:05:11 +0100 |
| commit | f0f352e97164692572ce41801abd62cf5641c44f (patch) | |
| tree | c5358515c45a5e1d62e8e66823559eaf942ac500 /techlibs/xilinx/cells_sim.v | |
| parent | ccfb4ff2a9d1cdf8205481042b0c22c39fc20e88 (diff) | |
| download | yosys-f0f352e97164692572ce41801abd62cf5641c44f.tar.gz yosys-f0f352e97164692572ce41801abd62cf5641c44f.tar.bz2 yosys-f0f352e97164692572ce41801abd62cf5641c44f.zip | |
[wip] sim model testing
Signed-off-by: David Shah <dave@ds0.me>
Diffstat (limited to 'techlibs/xilinx/cells_sim.v')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index a6ab98926..4e26ea5c9 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -728,7 +728,7 @@ module DSP48E1 ( maj_xyz_gated[23] ^ int_carry_out[1], 1'bx }; - end else if (USE_SIMD == "FOUR48") begin + end else begin assign maj_xyz_simd_gated = {maj_xyz_gated, alu_cin}; assign int_carry_in[3:1] = int_carry_out[2:0]; assign ext_carry_out = { @@ -738,7 +738,7 @@ module DSP48E1 ( end genvar i; - for (i = 0; i < 4; i++) + for (i = 0; i < 4; i = i + 1) assign {int_carry_out[i], alu_sum[i*12 +: 12]} = {1'b0, maj_xyz_simd_gated[i*12 +: ((i == 3) ? 13 : 12)]} + xor_xyz_muxed[i*12 +: 12] + int_carry_in[i]; endgenerate |