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| author | Marcin Kościelnicki <marcin@symbioticeda.com> | 2019-10-10 11:31:33 +0200 |
|---|---|---|
| committer | Marcin Kościelnicki <marcin@symbioticeda.com> | 2019-10-10 13:16:03 +0200 |
| commit | 526fe4cb89c912dee152e28a05f4ba3b5de6c3a3 (patch) | |
| tree | dca06d67e7dee8fcb894d3b6b6a53e924e94966f /techlibs/xilinx/cells_sim.v | |
| parent | 3fb604c75d3e8ee45d35fac8b787cb95a8adcf84 (diff) | |
| download | yosys-526fe4cb89c912dee152e28a05f4ba3b5de6c3a3.tar.gz yosys-526fe4cb89c912dee152e28a05f4ba3b5de6c3a3.tar.bz2 yosys-526fe4cb89c912dee152e28a05f4ba3b5de6c3a3.zip | |
xilinx: Add simulation model for IBUFG.
Diffstat (limited to 'techlibs/xilinx/cells_sim.v')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 28cd208cd..03985b1be 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -38,6 +38,17 @@ module IBUF( assign O = I; endmodule +module IBUFG( + output O, + (* iopad_external_pin *) + input I); + parameter CAPACITANCE = "DONT_CARE"; + parameter IBUF_DELAY_VALUE = "0"; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + assign O = I; +endmodule + module OBUF( (* iopad_external_pin *) output O, |