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| author | David Shah <dave@ds0.me> | 2019-08-08 11:32:43 +0100 |
|---|---|---|
| committer | David Shah <dave@ds0.me> | 2019-08-08 11:32:43 +0100 |
| commit | 57aeb4cc01058c0167e5a4eda9def97b0bb1741b (patch) | |
| tree | e21f3f0d1723188bababc3bca3f02199effe7784 /techlibs/xilinx/cells_sim.v | |
| parent | d60b3c0dc8ca9ce1b14c4acf2b602acc1fac00c5 (diff) | |
| download | yosys-57aeb4cc01058c0167e5a4eda9def97b0bb1741b.tar.gz yosys-57aeb4cc01058c0167e5a4eda9def97b0bb1741b.tar.bz2 yosys-57aeb4cc01058c0167e5a4eda9def97b0bb1741b.zip | |
DSP48E1 model: test CE inputs
Signed-off-by: David Shah <dave@ds0.me>
Diffstat (limited to 'techlibs/xilinx/cells_sim.v')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 13 |
1 files changed, 8 insertions, 5 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 53061808b..b738d9712 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -593,14 +593,17 @@ module DSP48E1 ( endgenerate wire signed [42:0] M = A_MULT * B_MULT; + wire signed [42:0] Mx = (CARRYINSEL == 3'b010) ? 43'bx : M; reg signed [42:0] Mr = 43'b0; // Multiplier result register generate - if (MREG == 1) begin always @(posedge CLK) if (RSTM) Mr <= 43'b0; else if (CEM) Mr <= M; end - else always @* Mr <= M; + if (MREG == 1) begin always @(posedge CLK) if (RSTM) Mr <= 43'b0; else if (CEM) Mr <= Mx; end + else always @* Mr <= Mx; endgenerate + wire signed [42:0] Mrx = (CARRYINSELr == 3'b010) ? 43'bx : Mr; + // X, Y and Z ALU inputs reg signed [47:0] X, Y, Z; @@ -608,7 +611,7 @@ module DSP48E1 ( // X multiplexer case (OPMODEr[1:0]) 2'b00: X = 48'b0; - 2'b01: begin X = $signed(Mr); + 2'b01: begin X = $signed(Mrx); `ifdef __ICARUS__ if (OPMODEr[3:2] != 2'b01) $fatal(1, "OPMODEr[3:2] must be 2'b01 when OPMODEr[1:0] is 2'b01"); `endif @@ -664,7 +667,7 @@ module DSP48E1 ( if (CARRYINREG == 1) begin always @(posedge CLK) if (RSTALLCARRYIN) CARRYINr <= 1'b0; else if (CECARRYIN) CARRYINr <= CARRYIN; end else always @* CARRYINr = CARRYIN; - if (MREG == 1) begin always @(posedge CLK) if (RSTALLCARRYIN) A24_xnor_B17 <= 1'b0; else if (CECARRYIN) A24_xnor_B17 <= A24_xnor_B17d; end + if (MREG == 1) begin always @(posedge CLK) if (RSTALLCARRYIN) A24_xnor_B17 <= 1'b0; else if (CEM) A24_xnor_B17 <= A24_xnor_B17d; end else always @* A24_xnor_B17 = A24_xnor_B17d; endgenerate @@ -755,7 +758,7 @@ module DSP48E1 ( wire [3:0] CARRYOUTd = (OPMODEr[3:0] == 4'b0101 || ALUMODEr[3:2] != 2'b00) ? 4'bxxxx : ((ALUMODEr[0] & ALUMODEr[1]) ? ~ext_carry_out : ext_carry_out); wire CARRYCASCOUTd = ext_carry_out[3]; - wire MULTSIGNOUTd = Mr[42]; + wire MULTSIGNOUTd = Mrx[42]; generate if (PREG == 1) begin |