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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-16 14:18:36 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-16 14:18:36 -0700 |
| commit | 569cd66764f43af9ea73038ce7437ab8557d497e (patch) | |
| tree | 6309ae90b08783f94e87e687f9688f94dc172358 /techlibs/xilinx/cells_sim.v | |
| parent | 9616dbd125171905bccf55fa7fd564e4ae2ca5ab (diff) | |
| parent | d38df68d26f1644539e5116e6b6c360e1c389cc9 (diff) | |
| download | yosys-569cd66764f43af9ea73038ce7437ab8557d497e.tar.gz yosys-569cd66764f43af9ea73038ce7437ab8557d497e.tar.bz2 yosys-569cd66764f43af9ea73038ce7437ab8557d497e.zip | |
Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp
Diffstat (limited to 'techlibs/xilinx/cells_sim.v')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 5410983ae..1262fc8c1 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -516,7 +516,7 @@ module DSP48E1 ( if (PCIN != 48'b0) $fatal(1, "Unsupported PCIN value"); if (CARRYIN != 1'b0) $fatal(1, "Unsupported CARRYIN value"); `endif - Pr[42:0] <= Ar[24:0] * Br; + Pr[42:0] <= $signed(Ar[24:0]) * $signed(Br); end generate |