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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-08 10:44:26 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-08 10:44:26 -0700 |
| commit | 13cc106cf7409570936f441af2cc133896f4ecb4 (patch) | |
| tree | 910f05718ad453c87aa37acf475d85b6bc79d43e /techlibs/xilinx/cells_sim.v | |
| parent | 0492b8b5412683392bc19ad7f15ba6c14e6668f8 (diff) | |
| download | yosys-13cc106cf7409570936f441af2cc133896f4ecb4.tar.gz yosys-13cc106cf7409570936f441af2cc133896f4ecb4.tar.bz2 yosys-13cc106cf7409570936f441af2cc133896f4ecb4.zip | |
Fix copy-pasta typo
Diffstat (limited to 'techlibs/xilinx/cells_sim.v')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 8b6eaae5d..2731cb454 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -522,7 +522,7 @@ module DSP48E1 ( always @* Ar2 <= A_muxed; end - // Configurable A register + // Configurable B register if (BREG == 2) begin always @(posedge CLK) if (RSTB) begin @@ -532,7 +532,7 @@ module DSP48E1 ( if (CEB1) Br1 <= B_muxed; if (CEB2) Br2 <= Br1; end - end else if (AREG == 1) begin + end else if (BREG == 1) begin always @(posedge CLK) if (RSTB) begin Br1 <= 18'b0; |