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| author | David Shah <dave@ds0.me> | 2019-08-08 10:26:40 +0100 |
|---|---|---|
| committer | David Shah <dave@ds0.me> | 2019-08-08 10:26:44 +0100 |
| commit | f6605c7dc0b1bcbc091b8283a741e24be25478b1 (patch) | |
| tree | 84d6d97f7c3d740de93a56f39ee7d27a234dfc9f /techlibs/xilinx/cells_sim.v | |
| parent | f0f352e97164692572ce41801abd62cf5641c44f (diff) | |
| download | yosys-f6605c7dc0b1bcbc091b8283a741e24be25478b1.tar.gz yosys-f6605c7dc0b1bcbc091b8283a741e24be25478b1.tar.bz2 yosys-f6605c7dc0b1bcbc091b8283a741e24be25478b1.zip | |
DSP48E1 sim model: Comb, no pre-adder, mode working
Signed-off-by: David Shah <dave@ds0.me>
Diffstat (limited to 'techlibs/xilinx/cells_sim.v')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 4e26ea5c9..3817c6a1d 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -689,7 +689,7 @@ module DSP48E1 ( // ALU core wire [47:0] Z_muxinv = ALUMODEr[0] ? ~Z : Z; wire [47:0] xor_xyz = X ^ Y ^ Z_muxinv; - wire [47:0] maj_xyz = (X & Y) | (X & Z) | (X & Y); + wire [47:0] maj_xyz = (X & Y) | (X & Z_muxinv) | (Y & Z_muxinv); wire [47:0] xor_xyz_muxed = ALUMODEr[3] ? maj_xyz : xor_xyz; wire [47:0] maj_xyz_gated = ALUMODEr[2] ? 48'b0 : maj_xyz; @@ -745,7 +745,8 @@ module DSP48E1 ( wire signed [47:0] Pd = ALUMODEr[1] ? ~alu_sum : alu_sum; initial P = 48'b0; - wire [3:0] CARRYOUTd = (ALUMODEr[0] & ALUMODEr[1]) ? ~ext_carry_out : ext_carry_out; + wire [3:0] CARRYOUTd = (OPMODEr[3:0] == 4'b0101 || ALUMODEr[3:2] != 2'b00) ? 4'bxxxx : + ((ALUMODEr[0] & ALUMODEr[1]) ? ~ext_carry_out : ext_carry_out); wire CARRYCASCOUTd = ext_carry_out[3]; wire MULTSIGNOUTd = Mr[42]; |