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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-13 12:19:26 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-13 12:19:26 -0700 |
| commit | ed4b2834ef6ed811318c897bd6f8b19b6ec15f38 (patch) | |
| tree | 8bab1632852b98f3c9b823700ddeffacd837191c /techlibs/xilinx/cells_sim.v | |
| parent | 0597a3ea238ee100607271fb25a2d09fbd128bf0 (diff) | |
| download | yosys-ed4b2834ef6ed811318c897bd6f8b19b6ec15f38.tar.gz yosys-ed4b2834ef6ed811318c897bd6f8b19b6ec15f38.tar.bz2 yosys-ed4b2834ef6ed811318c897bd6f8b19b6ec15f38.zip | |
Add assign PCOUT = P to DSP48E1
Diffstat (limited to 'techlibs/xilinx/cells_sim.v')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 2731cb454..02ce0d61b 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -784,4 +784,6 @@ module DSP48E1 ( end endgenerate + assign PCOUT = P; + endmodule |