| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| | * | | xilinx: Add correct signed behaviour to DSP48E1 model | David Shah | 2019-07-16 | 1 | -1/+1 | |
| | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| * | | | Add support for {A,B,P}REG in DSP48E1 | Eddie Hung | 2019-07-16 | 1 | -5/+21 | |
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| * / | Move DSP48E1 model out of cells_xtra, initial multiply one in cells_sim | Eddie Hung | 2019-07-15 | 1 | -0/+131 | |
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| * | xilinx: Fix the default values for FDPE/FDSE INIT attributes to match ↵ | Marcin Kościelnicki | 2019-07-11 | 1 | -2/+2 | |
| | | | | | ISE/Vivado. | |||||
| * | Revert "Fix broken MUXFx box, use MUXF7x2 box instead" | Eddie Hung | 2019-07-01 | 1 | -3/+3 | |
| | | | | | This reverts commit a9a140aa6c84e71edc1a244cfe363400c7e09d90. | |||||
| * | Fix broken MUXFx box, use MUXF7x2 box instead | Eddie Hung | 2019-07-01 | 1 | -3/+3 | |
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| * | Fix CARRY4 abc_box_id | Eddie Hung | 2019-06-28 | 1 | -1/+1 | |
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| * | Merge remote-tracking branch 'origin/master' into xc7mux | Eddie Hung | 2019-06-28 | 1 | -2/+2 | |
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| | * | Refactor for one "abc_carry" attribute on module | Eddie Hung | 2019-06-27 | 1 | -2/+2 | |
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| | * | Merge origin/master | Eddie Hung | 2019-06-27 | 1 | -1/+1 | |
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| * | | Merge remote-tracking branch 'origin/xaig' into xc7mux | Eddie Hung | 2019-06-26 | 1 | -3/+3 | |
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| | * | Add "WE" to dist RAM's abc_scc_break | Eddie Hung | 2019-06-26 | 1 | -3/+3 | |
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| | * | Add RAM32X1D box info | Eddie Hung | 2019-06-25 | 1 | -2/+3 | |
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| | * | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-06-25 | 1 | -0/+17 | |
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| * | \ | Merge remote-tracking branch 'origin/eddie/fix1132' into xc7mux | Eddie Hung | 2019-06-26 | 1 | -1/+1 | |
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| | * | | | Simulation model verilog fix | Miodrag Milanovic | 2019-06-26 | 1 | -1/+1 | |
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| * | | | Cleanup abc_box_id | Eddie Hung | 2019-06-26 | 1 | -5/+5 | |
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| * | | | Add RAM32X1D box info | Eddie Hung | 2019-06-24 | 1 | -2/+3 | |
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| * | | | Merge remote-tracking branch 'origin/xaig' into xc7mux | Eddie Hung | 2019-06-24 | 1 | -0/+2 | |
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| | * | | Add Xilinx dist RAM as comb boxes | Eddie Hung | 2019-06-24 | 1 | -0/+2 | |
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| * | | | Merge remote-tracking branch 'origin/eddie/ram32x1d' into xc7mux | Eddie Hung | 2019-06-24 | 1 | -0/+17 | |
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| | * | | Add RAM32X1D support | Eddie Hung | 2019-06-24 | 1 | -0/+17 | |
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| * | | | Merge remote-tracking branch 'origin/xaig' into xc7mux | Eddie Hung | 2019-06-22 | 1 | -2/+0 | |
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| | * | | Remove DFF and RAMD box info for now | Eddie Hung | 2019-06-21 | 1 | -2/+0 | |
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| * | | | Add $__XILINX_MUXF78 to preserve entire box | Eddie Hung | 2019-06-21 | 1 | -0/+8 | |
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| * | | Remove WIP ABC9 flop support | Eddie Hung | 2019-06-14 | 1 | -10/+10 | |
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| * | | Disable dist RAM boxes due to comb loop | Eddie Hung | 2019-06-11 | 1 | -2/+2 | |
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| * | | Remove #ifndef ABC | Eddie Hung | 2019-06-11 | 1 | -4/+0 | |
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| * | | Remove abc_flop attributes for now | Eddie Hung | 2019-06-06 | 1 | -56/+10 | |
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| * | | Update abc attributes on FD*E_1 | Eddie Hung | 2019-06-05 | 1 | -6/+26 | |
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| * | | Typo | Eddie Hung | 2019-06-03 | 1 | -1/+1 | |
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| * | | Fix `ifndef | Eddie Hung | 2019-06-03 | 1 | -1/+1 | |
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| * | | Add FD*E_1 -> FD*E techmap rules | Eddie Hung | 2019-05-31 | 1 | -5/+31 | |
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| * | | Remove whitebox attribute from DRAMs for now | Eddie Hung | 2019-05-30 | 1 | -2/+2 | |
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| * | | Carry in/out to be the last input/output for chains to be preserved | Eddie Hung | 2019-05-30 | 1 | -2/+2 | |
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| * | | Re-enable lib_whitebox | Eddie Hung | 2019-05-27 | 1 | -5/+5 | |
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| * | | Blackboxes | Eddie Hung | 2019-05-26 | 1 | -5/+5 | |
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| * | | Add whitebox support to DRAM | Eddie Hung | 2019-05-23 | 1 | -2/+8 | |
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| * | | Instead of MUXCY/XORCY use CARRY4 (with timing) | Eddie Hung | 2019-05-21 | 1 | -2/+1 | |
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| * | | Cleanup, call pmux2shiftx even without -nosrl | Eddie Hung | 2019-04-22 | 1 | -12/+16 | |
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| * | Merge remote-tracking branch 'origin' into xc7srl | Eddie Hung | 2019-04-20 | 1 | -0/+57 | |
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| | * | Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra. | Keith Rothman | 2019-04-12 | 1 | -11/+11 | |
| | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | |||||
| | * | Fix LUT6_2 definition. | Keith Rothman | 2019-04-09 | 1 | -3/+3 | |
| | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | |||||
| | * | Add additional cells sim models for core 7-series primatives. | Keith Rothman | 2019-04-09 | 1 | -0/+57 | |
| | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | |||||
| * | | Merge remote-tracking branch 'origin/master' into xc7srl | Eddie Hung | 2019-03-14 | 1 | -0/+65 | |
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| | * | Revert FF models to include IS_x_INVERTED parameters. | Keith Rothman | 2019-03-01 | 1 | -6/+34 | |
| | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | |||||
| | * | Changes required for VPR place and route synth_xilinx. | Keith Rothman | 2019-03-01 | 1 | -33/+70 | |
| | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | |||||
| * | | Add SRL16 and SRL32 sim models | Eddie Hung | 2019-02-28 | 1 | -0/+39 | |
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| * | Add Xilinx RAM64X1D and RAM128X1D simulation models | Clifford Wolf | 2018-03-07 | 1 | -0/+30 | |
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| * | Disabled (unused) Xilinx tristate buffers | Clifford Wolf | 2015-02-04 | 1 | -6/+6 | |
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index : iCE40/yosys | |
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