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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-11 12:02:31 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-11 12:02:31 -0700 |
| commit | 8a708d1fdb662f86a46720200fa15acafde30333 (patch) | |
| tree | 2c803e176976e86cc9d21006b09eb6b7f921364c /techlibs/xilinx/cells_sim.v | |
| parent | a138381ac3f2c820d187f08531ffd823d6cbcfd5 (diff) | |
| download | yosys-8a708d1fdb662f86a46720200fa15acafde30333.tar.gz yosys-8a708d1fdb662f86a46720200fa15acafde30333.tar.bz2 yosys-8a708d1fdb662f86a46720200fa15acafde30333.zip | |
Remove #ifndef ABC
Diffstat (limited to 'techlibs/xilinx/cells_sim.v')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 88967b068..14e35737e 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -295,10 +295,8 @@ module RAM64X1D ( reg [63:0] mem = INIT; assign SPO = mem[a]; assign DPO = mem[dpra]; -`ifndef _ABC wire clk = WCLK ^ IS_WCLK_INVERTED; always @(posedge clk) if (WE) mem[a] <= D; -`endif endmodule (* abc_box_id = 5 /*, lib_whitebox*/ *) @@ -312,10 +310,8 @@ module RAM128X1D ( reg [127:0] mem = INIT; assign SPO = mem[A]; assign DPO = mem[DPRA]; -`ifndef _ABC wire clk = WCLK ^ IS_WCLK_INVERTED; always @(posedge clk) if (WE) mem[A] <= D; -`endif endmodule module SRL16E ( |