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* Update Xilinx cell definitions, fixes #3699Miodrag Milanovic2023-03-231-3/+8
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* Check DREG attributeOliver Keszöcze2023-02-171-1/+1
| | | The DSP48E1 implementation checked the wrong attribute (i.e. CREG) to initialize the D input register. This PR fixes 3680
* Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-081-1/+1
| | | | | | | | s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
* xilinx: Add FDRSE_1, FDCPE_1.Marcelina Kościelnicka2021-01-271-0/+80
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* xilinx: Add some missing blackbox cells.Marcelina Kościelnicka2020-12-211-0/+99
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* Move signal declarations to before first useJeff Goeders2020-10-191-2/+2
| | | | Signed-off-by: Jeff Goeders <jeff.goeders@gmail.com>
* xilinx: do not make DSP48E1 a whitebox for ABC9 by default (#2325)Eddie Hung2020-09-231-17/+64
| | | | | | | | | | | * xilinx: eliminate SCCs from DSP48E1 model * xilinx: add SCC test for DSP48E1 * Update techlibs/xilinx/cells_sim.v * xilinx: Gate DSP48E1 being a whitebox behind ALLOW_WHITEBOX_DSP48E1 Have a test that checks it works through ABC9 when enabled
* Remove EXPLICIT_CARRY logic.Keith Rothman2020-07-231-23/+0
| | | | | | | The symbiflow-arch-defs tool chain no longer needs the EXPLICIT_CARRY within yosys itself. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* xilinx: tidy up cells_sim.v a littleEddie Hung2020-05-251-5/+7
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* xilinx: gate specify/attributes from iverilogEddie Hung2020-05-141-1/+3
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* xilinx/ecp5/ice40: add (* abc9_flop *) to bypass-able cellsEddie Hung2020-05-141-1/+19
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* abc9_ops: add -prep_bypass for auto bypass boxes; refactorEddie Hung2020-05-141-96/+126
| | | | | Eliminate need for abc9_{,un}map.v in xilinx -prep_dff_{hier,unmap} -> -prep_hier
* abc9_ops: -prep_dff_map to error if async flop foundEddie Hung2020-05-141-4/+0
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* Uncomment negative setup times; clamp to zero for connectivityEddie Hung2020-05-141-13/+29
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* abc9_ops: add 'dff' label for auto handling of (* abc9_flop *) boxesEddie Hung2020-05-141-4/+4
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* xilinx: consider DSP48E1.ADREGEddie Hung2020-03-041-3/+3
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* xilinx: improve specify for DSP48E1Eddie Hung2020-03-041-32/+116
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* xilinx: Update RAMB* specify entriesEddie Hung2020-02-271-11/+42
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* xilinx: add delays to INVEddie Hung2020-02-271-0/+3
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* Make +/xilinx/cells_sim.v legalEddie Hung2020-02-271-76/+78
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* Get rid of (* abc9_{arrival,required} *) entirelyEddie Hung2020-02-271-80/+492
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* Expand +/xilinx/cells_sim.v to keep ICARUS and non -specify paresr happyEddie Hung2020-02-271-14/+12
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* Fix tests by gating some specify constructs from iverilogEddie Hung2020-02-271-0/+16
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* abc9_ops: ignore (* abc9_flop *) if not '-dff'Eddie Hung2020-02-271-2/+6
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* Update xilinx for ABC9Eddie Hung2020-02-271-8/+15
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* Fix commented out specify statementEddie Hung2020-02-271-6/+6
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* xilinx: improve specify functionalityEddie Hung2020-02-271-420/+445
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* xilinx: use specify blocks in place of abc9_{arrival,required}Eddie Hung2020-02-271-176/+404
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* Auto-generate .box/.lut files from specify blocksEddie Hung2020-02-271-3/+70
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* abc9_ops: -prep_lut and -write_lut to auto-generate LUT libraryEddie Hung2020-02-271-0/+83
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* Merge pull request #1661 from YosysHQ/eddie/abc9_requiredEddie Hung2020-02-051-81/+314
|\ | | | | abc9: add support for required times
| * abc9_ops: generate flop box ids, add abc9_required to FD* cellsEddie Hung2020-01-141-12/+45
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| * Add abc9_required to DSP48E1.{A,B,C,D,PCIN}Eddie Hung2020-01-101-38/+117
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| * Merge remote-tracking branch 'origin/eddie/abc9_refactor' into ↵Eddie Hung2020-01-081-3/+80
| |\ | | | | | | | | | eddie/abc9_required
| * \ Merge remote-tracking branch 'origin/eddie/abc9_refactor' into ↵Eddie Hung2020-01-061-59/+68
| |\ \ | | | | | | | | | | | | xaig_arrival_required
| * | | Update some abc9_arrival times, add abc9_required timesEddie Hung2019-12-271-24/+164
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* | | | xilinx: Add simulation model for DSP48 (Virtex 4).Marcin Kościelnicki2020-01-291-1/+229
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* | | Merge branch 'master' of github.com:YosysHQ/yosysEddie Hung2020-01-061-51/+59
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| * \ \ Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2020-01-061-0/+77
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| * | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2020-01-021-21/+41
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| * | | | Re-arrange FD orderEddie Hung2019-12-311-77/+77
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| * | | | FDCE ports to be alphabeticalEddie Hung2019-12-311-3/+3
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| * | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-301-3/+3
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| * | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-201-24/+10
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| * \ \ \ \ Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-201-4/+197
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| * | | | | | Split into $__ABC9_ASYNC[01], do not add cell->type to clkdomain_tEddie Hung2019-12-191-8/+8
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| * | | | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-191-12/+47
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| * \ \ \ \ \ \ Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-061-0/+797
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| * | | | | | | | Oh deary meEddie Hung2019-12-041-4/+4
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| * | | | | | | | Merge remote-tracking branch 'origin/eddie/write_xaiger_improve' into xaig_dffEddie Hung2019-11-271-0/+28
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