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| author | Eddie Hung <eddie@fpgeh.com> | 2019-05-30 01:23:36 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-05-30 01:23:36 -0700 |
| commit | fdfc18be91123e2939f134dafc12e1e0c1a82f7b (patch) | |
| tree | f5feea08b0bc644a5474f333944eaea1f78d9ee1 /techlibs/xilinx/cells_sim.v | |
| parent | 8c58c728a79954603289abf3520139da0a9bbb26 (diff) | |
| download | yosys-fdfc18be91123e2939f134dafc12e1e0c1a82f7b.tar.gz yosys-fdfc18be91123e2939f134dafc12e1e0c1a82f7b.tar.bz2 yosys-fdfc18be91123e2939f134dafc12e1e0c1a82f7b.zip | |
Carry in/out to be the last input/output for chains to be preserved
Diffstat (limited to 'techlibs/xilinx/cells_sim.v')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 29c79f689..120370860 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -173,8 +173,8 @@ module XORCY(output O, input CI, LI); assign O = CI ^ LI; endmodule -(* abc_box_id = 3, lib_whitebox *) -module CARRY4(output [3:0] CO, O, input CI, CYINIT, input [3:0] DI, S); +(* abc_box_id = 3, lib_whitebox, abc_carry *) +module CARRY4((* abc_carry_out *) output [3:0] CO, output [3:0] O, (* abc_carry_in *) input CI, input CYINIT, input [3:0] DI, S); assign O = S ^ {CO[2:0], CI | CYINIT}; assign CO[0] = S[0] ? CI | CYINIT : DI[0]; assign CO[1] = S[1] ? CO[0] : DI[1]; |