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| author | Eddie Hung <eddie@fpgeh.com> | 2019-05-21 16:19:45 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-05-21 16:19:45 -0700 |
| commit | ee8435b820bbea4a4ceb2c46a81de9d03d4aa44c (patch) | |
| tree | 15c24a82884ffd0fabdd24ddfc48e2c16b08d583 /techlibs/xilinx/cells_sim.v | |
| parent | 0f094fba08b69baa2329e749daf19f41a624a0a0 (diff) | |
| download | yosys-ee8435b820bbea4a4ceb2c46a81de9d03d4aa44c.tar.gz yosys-ee8435b820bbea4a4ceb2c46a81de9d03d4aa44c.tar.bz2 yosys-ee8435b820bbea4a4ceb2c46a81de9d03d4aa44c.zip | |
Instead of MUXCY/XORCY use CARRY4 (with timing)
Diffstat (limited to 'techlibs/xilinx/cells_sim.v')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 8b231480f..9db52b67a 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -155,7 +155,6 @@ module LUT6_2(output O6, output O5, input I0, I1, I2, I3, I4, I5); assign O5 = I0 ? s5_1[1] : s5_1[0]; endmodule -(* abc_box_id = 3, lib_whitebox *) module MUXCY(output O, input CI, DI, S); assign O = S ? CI : DI; endmodule @@ -170,11 +169,11 @@ module MUXF8(output O, input I0, I1, S); assign O = S ? I1 : I0; endmodule -(* abc_box_id = 4, lib_whitebox *) module XORCY(output O, input CI, LI); assign O = CI ^ LI; endmodule +(* abc_box_id = 3, lib_whitebox *) module CARRY4(output [3:0] CO, O, input CI, CYINIT, input [3:0] DI, S); assign O = S ^ {CO[2:0], CI | CYINIT}; assign CO[0] = S[0] ? CI | CYINIT : DI[0]; |