aboutsummaryrefslogtreecommitdiffstats
path: root/techlibs/xilinx/cells_sim.v
Commit message (Expand)AuthorAgeFilesLines
* xilinx: Fix the default values for FDPE/FDSE INIT attributes to match ISE/Viv...Marcin Kościelnicki2019-07-111-2/+2
* Revert "Fix broken MUXFx box, use MUXF7x2 box instead"Eddie Hung2019-07-011-3/+3
* Fix broken MUXFx box, use MUXF7x2 box insteadEddie Hung2019-07-011-3/+3
* Fix CARRY4 abc_box_idEddie Hung2019-06-281-1/+1
* Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-06-281-2/+2
|\
| * Refactor for one "abc_carry" attribute on moduleEddie Hung2019-06-271-2/+2
| * Merge origin/masterEddie Hung2019-06-271-1/+1
* | Merge remote-tracking branch 'origin/xaig' into xc7muxEddie Hung2019-06-261-3/+3
|\|
| * Add "WE" to dist RAM's abc_scc_breakEddie Hung2019-06-261-3/+3
| * Add RAM32X1D box infoEddie Hung2019-06-251-2/+3
| * Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-06-251-0/+17
| |\
* | \ Merge remote-tracking branch 'origin/eddie/fix1132' into xc7muxEddie Hung2019-06-261-1/+1
|\ \ \
| * | | Simulation model verilog fixMiodrag Milanovic2019-06-261-1/+1
| | |/ | |/|
* | | Cleanup abc_box_idEddie Hung2019-06-261-5/+5
* | | Add RAM32X1D box infoEddie Hung2019-06-241-2/+3
* | | Merge remote-tracking branch 'origin/xaig' into xc7muxEddie Hung2019-06-241-0/+2
|\ \ \ | | |/ | |/|
| * | Add Xilinx dist RAM as comb boxesEddie Hung2019-06-241-0/+2
* | | Merge remote-tracking branch 'origin/eddie/ram32x1d' into xc7muxEddie Hung2019-06-241-0/+17
|\ \ \ | | |/ | |/|
| * | Add RAM32X1D supportEddie Hung2019-06-241-0/+17
* | | Merge remote-tracking branch 'origin/xaig' into xc7muxEddie Hung2019-06-221-2/+0
|\ \ \ | | |/ | |/|
| * | Remove DFF and RAMD box info for nowEddie Hung2019-06-211-2/+0
* | | Add $__XILINX_MUXF78 to preserve entire boxEddie Hung2019-06-211-0/+8
|/ /
* | Remove WIP ABC9 flop supportEddie Hung2019-06-141-10/+10
* | Disable dist RAM boxes due to comb loopEddie Hung2019-06-111-2/+2
* | Remove #ifndef ABCEddie Hung2019-06-111-4/+0
* | Remove abc_flop attributes for nowEddie Hung2019-06-061-56/+10
* | Update abc attributes on FD*E_1Eddie Hung2019-06-051-6/+26
* | TypoEddie Hung2019-06-031-1/+1
* | Fix `ifndefEddie Hung2019-06-031-1/+1
* | Add FD*E_1 -> FD*E techmap rulesEddie Hung2019-05-311-5/+31
* | Remove whitebox attribute from DRAMs for nowEddie Hung2019-05-301-2/+2
* | Carry in/out to be the last input/output for chains to be preservedEddie Hung2019-05-301-2/+2
* | Re-enable lib_whiteboxEddie Hung2019-05-271-5/+5
* | BlackboxesEddie Hung2019-05-261-5/+5
* | Add whitebox support to DRAMEddie Hung2019-05-231-2/+8
* | Instead of MUXCY/XORCY use CARRY4 (with timing)Eddie Hung2019-05-211-2/+1
* | Cleanup, call pmux2shiftx even without -nosrlEddie Hung2019-04-221-12/+16
|/
* Merge remote-tracking branch 'origin' into xc7srlEddie Hung2019-04-201-0/+57
|\
| * Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra.Keith Rothman2019-04-121-11/+11
| * Fix LUT6_2 definition.Keith Rothman2019-04-091-3/+3
| * Add additional cells sim models for core 7-series primatives.Keith Rothman2019-04-091-0/+57
* | Merge remote-tracking branch 'origin/master' into xc7srlEddie Hung2019-03-141-0/+65
|\|
| * Revert FF models to include IS_x_INVERTED parameters.Keith Rothman2019-03-011-6/+34
| * Changes required for VPR place and route synth_xilinx.Keith Rothman2019-03-011-33/+70
* | Add SRL16 and SRL32 sim modelsEddie Hung2019-02-281-0/+39
|/
* Add Xilinx RAM64X1D and RAM128X1D simulation modelsClifford Wolf2018-03-071-0/+30
* Disabled (unused) Xilinx tristate buffersClifford Wolf2015-02-041-6/+6
* Added Xilinx example for Basys3 boardClifford Wolf2015-02-011-1/+5
* Fixed xilinx FDSE sim modelClifford Wolf2015-01-241-2/+2
* Added MUXCY and XORCY support to synth_xilinxClifford Wolf2015-01-171-0/+4
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-06 08:31:26 +0000