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* simul: finalize empty proceduresTristan Gingold2022-10-011-9/+11
* simul: minor rewriteTristan Gingold2022-10-011-3/+2
* simul: finalize declarations of procedure callsTristan Gingold2022-10-011-0/+4
* simul: handle stable attributeTristan Gingold2022-09-302-5/+44
* synth: factorize codeTristan Gingold2022-09-301-0/+8
* simul: create disconnectionsTristan Gingold2022-09-301-1/+42
* simul: handle quiet attributeTristan Gingold2022-09-292-7/+72
* simul: factorize code, add sub_signal_typeTristan Gingold2022-09-294-92/+73
* simul: support guarded signal assignments (WIP)Tristan Gingold2022-09-291-8/+79
* synth: handle guard signal in debuggerTristan Gingold2022-09-281-56/+65
* simul: handle last_value attributeTristan Gingold2022-09-281-1/+23
* simul: fix handling of labels in next/exit statementsTristan Gingold2022-09-281-4/+13
* synth: handle null-range loopsTristan Gingold2022-09-281-4/+3
* simul: handle null signal assignmentsTristan Gingold2022-09-271-12/+36
* simul-vhdl_elab: avoid a crash for null-range signalsTristan Gingold2022-09-261-10/+14
* synth: handle attributes in configurationsTristan Gingold2022-09-262-2/+4
* synth: rework error procedure, always pass the instanceTristan Gingold2022-09-251-1/+1
* simul: gather disconnection specifications, create guard signalTristan Gingold2022-09-253-33/+191
* synth: ignore groups and group templatesTristan Gingold2022-09-251-1/+3
* simul: handle empty proceduresTristan Gingold2022-09-251-1/+9
* synth: rework association conversionsTristan Gingold2022-09-251-34/+11
* simul: reuse drivers extraction from elaborationTristan Gingold2022-09-252-74/+26
* synth-vhdl_stmts: minor renamingTristan Gingold2022-09-181-2/+2
* simul: handle individual port associations with expressionsTristan Gingold2022-09-181-1/+5
* simul: handle type conversions in port associationsTristan Gingold2022-09-181-11/+17
* simul: fix resolved associationTristan Gingold2022-09-172-2/+3
* simul: use synth_declarations for processes and proceduresTristan Gingold2022-09-172-5/+4
* synth: factorize code (reuse synth_constant_declaration)Tristan Gingold2022-09-172-2/+2
* synth: handle protected types in subprogramsTristan Gingold2022-09-171-31/+3
* synth: preliminary work to factorize codeTristan Gingold2022-09-161-13/+5
* simul: handle active attributeTristan Gingold2022-09-161-10/+49
* simul: improve support of concurrent procedure callTristan Gingold2022-09-161-1/+20
* simul: improve error handling during elaborationTristan Gingold2022-09-161-0/+1
* simul: handle more signals typesTristan Gingold2022-09-152-23/+128
* simul: factorize code for conversion functionsTristan Gingold2022-09-121-19/+6
* simul: do not consider signal parameters as dynamic valuesTristan Gingold2022-09-121-0/+1
* simul: move assertions (not to trigger in case of errors)Tristan Gingold2022-09-111-3/+3
* simul: optimize resolution call only for std_logicTristan Gingold2022-09-111-5/+11
* synth: fix and add checks for memory management.Tristan Gingold2022-09-101-6/+17
* simul: add support for protected objectsTristan Gingold2022-09-082-2/+62
* elab-vhdl_values: factorize codeTristan Gingold2022-09-071-2/+2
* simul: do not propagate errors from resolution functionTristan Gingold2022-09-071-0/+3
* simul: fix computation for number of driversTristan Gingold2022-09-061-1/+2
* synth: handle generics in blocksTristan Gingold2022-09-062-3/+21
* simul: add an hook to display report/assert messageTristan Gingold2022-09-061-14/+50
* synth: use areapoolsTristan Gingold2022-09-023-90/+139
* synth: factorize code for tracing statements executionTristan Gingold2022-09-021-3/+7
* simul: detect multiple drivers for unresolved signalsTristan Gingold2022-09-021-8/+93
* simul-vhdl_simul: simplify procedure connectTristan Gingold2022-08-261-41/+22
* simul: handle connections of recordsTristan Gingold2022-08-251-1/+18
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