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| author | Tristan Gingold <tgingold@free.fr> | 2022-09-18 05:33:29 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-09-18 05:33:29 +0200 |
| commit | b3b31cc9b74b3f1bc07b15ada32ba2925eb490df (patch) | |
| tree | 55afc7694bbb00f4c4f2184803612ea833d87c3c /src/simul | |
| parent | 8e7a8b63b190ca32f5f0606a04e56b9d5289ca47 (diff) | |
| download | ghdl-b3b31cc9b74b3f1bc07b15ada32ba2925eb490df.tar.gz ghdl-b3b31cc9b74b3f1bc07b15ada32ba2925eb490df.tar.bz2 ghdl-b3b31cc9b74b3f1bc07b15ada32ba2925eb490df.zip | |
simul: handle individual port associations with expressions
Diffstat (limited to 'src/simul')
| -rw-r--r-- | src/simul/simul-vhdl_elab.adb | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/simul/simul-vhdl_elab.adb b/src/simul/simul-vhdl_elab.adb index b400a8106..b00cba063 100644 --- a/src/simul/simul-vhdl_elab.adb +++ b/src/simul/simul-vhdl_elab.adb @@ -629,8 +629,12 @@ package body Simul.Vhdl_Elab is null; when Iir_Kind_Association_Element_By_Expression => Inter := Get_Association_Interface (Assoc, Assoc_Inter); + Formal := Get_Formal (Assoc); + if Formal = Null_Iir then + Formal := Inter; + end if; Synth_Assignment_Prefix - (Port_Inst, Inter, Formal_Base, Typ, Off); + (Port_Inst, Formal, Formal_Base, Typ, Off); Formal_Sig := Formal_Base.Val.S; Formal_Ep := (Formal_Sig, Off, Typ); |