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author | Tristan Gingold <tgingold@free.fr> | 2022-08-28 10:27:25 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2022-09-02 02:31:06 +0200 |
commit | 91303467eac522662572d9106e2a3cb724b24a0d (patch) | |
tree | 42225eb45dd10fa38a47f4bacebe82bfb6cb3934 /src/simul | |
parent | 50f1990e59efaf927658c354aa6e2c81461964da (diff) | |
download | ghdl-91303467eac522662572d9106e2a3cb724b24a0d.tar.gz ghdl-91303467eac522662572d9106e2a3cb724b24a0d.tar.bz2 ghdl-91303467eac522662572d9106e2a3cb724b24a0d.zip |
synth: factorize code for tracing statements execution
Diffstat (limited to 'src/simul')
-rw-r--r-- | src/simul/simul-vhdl_simul.adb | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/src/simul/simul-vhdl_simul.adb b/src/simul/simul-vhdl_simul.adb index 4046b3dd0..1fe1f76a3 100644 --- a/src/simul/simul-vhdl_simul.adb +++ b/src/simul/simul-vhdl_simul.adb @@ -36,11 +36,12 @@ with PSL.NFAs; with PSL.NFAs.Utils; with PSL.Errors; +with Elab.Debugger; with Elab.Vhdl_Objtypes; use Elab.Vhdl_Objtypes; with Elab.Vhdl_Values; use Elab.Vhdl_Values; with Elab.Vhdl_Types; with Elab.Vhdl_Decls; -with Elab.Debugger; +with Elab.Vhdl_Debug; with Trans_Analyzes; @@ -954,6 +955,9 @@ package body Simul.Vhdl_Simul is loop Inst := Process.Instance; + if Synth.Flags.Flag_Trace_Statements then + Elab.Vhdl_Debug.Put_Stmt_Trace (Stmt); + end if; if Elab.Debugger.Flag_Need_Debug then Elab.Debugger.Debug_Break (Inst, Stmt); end if; @@ -1272,8 +1276,8 @@ package body Simul.Vhdl_Simul is -- Instance_Pool := Process.Pool'Access; if Synth.Flags.Flag_Trace_Statements then - Put (" run process: "); --- Disp_Instance_Name (Process.Top_Instance); + Put ("run process: "); + Elab.Vhdl_Debug.Disp_Instance_Path (Process.Top_Instance); Put_Line (" (" & Vhdl.Errors.Disp_Location (Process.Proc) & ")"); end if; |