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| author | Tristan Gingold <tgingold@free.fr> | 2022-09-28 06:43:44 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-09-28 06:43:44 +0200 |
| commit | 5993986a91f3f41813b890e6b9d10cc5a3beea17 (patch) | |
| tree | abc04887c28d2784983f80d7ed161a7d1a19ea5b /src/simul | |
| parent | e15f01013928d7023a1f6d4bc93aa59fef9bffcf (diff) | |
| download | ghdl-5993986a91f3f41813b890e6b9d10cc5a3beea17.tar.gz ghdl-5993986a91f3f41813b890e6b9d10cc5a3beea17.tar.bz2 ghdl-5993986a91f3f41813b890e6b9d10cc5a3beea17.zip | |
synth: handle null-range loops
Diffstat (limited to 'src/simul')
| -rw-r--r-- | src/simul/simul-vhdl_simul.adb | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/src/simul/simul-vhdl_simul.adb b/src/simul/simul-vhdl_simul.adb index 341e574d8..95048757b 100644 --- a/src/simul/simul-vhdl_simul.adb +++ b/src/simul/simul-vhdl_simul.adb @@ -533,15 +533,14 @@ package body Simul.Vhdl_Simul is Param : constant Node := Get_Parameter_Specification (Parent); Val : Valtyp; + Valid : Boolean; begin -- Update index Val := Get_Value (Process.Instance, Param); - Update_Index (Val.Typ.Drange, Val); + Update_Index (Val.Typ.Drange, Valid, Val); -- Test. - if Elab.Vhdl_Objtypes.In_Range (Val.Typ.Drange, - Read_Discrete (Val)) - then + if Valid then Stmt := Get_Sequential_Statement_Chain (Parent); return; end if; |