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| author | Tristan Gingold <tgingold@free.fr> | 2022-09-07 04:48:11 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-09-07 04:48:11 +0200 |
| commit | 68a7010349341dfaa8aa7b8b27701bf639ea0857 (patch) | |
| tree | 7bbe7fc82070207d3d9d8f5a62ac7de63ac8e522 /src/simul | |
| parent | 3136726f2b52be19d31146a2427f54b0f0718f33 (diff) | |
| download | ghdl-68a7010349341dfaa8aa7b8b27701bf639ea0857.tar.gz ghdl-68a7010349341dfaa8aa7b8b27701bf639ea0857.tar.bz2 ghdl-68a7010349341dfaa8aa7b8b27701bf639ea0857.zip | |
simul: do not propagate errors from resolution function
Diffstat (limited to 'src/simul')
| -rw-r--r-- | src/simul/simul-vhdl_simul.adb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/simul/simul-vhdl_simul.adb b/src/simul/simul-vhdl_simul.adb index a9393b277..856f18a0b 100644 --- a/src/simul/simul-vhdl_simul.adb +++ b/src/simul/simul-vhdl_simul.adb @@ -2341,6 +2341,9 @@ package body Simul.Vhdl_Simul is Create_Value_Memory (Val)); Res := Synth.Vhdl_Expr.Synth_Subtype_Conversion (Inst, Res, Res_Typ, False, Func); + if Res = No_Valtyp then + Grt.Errors.Fatal_Error; + end if; return Synth.Vhdl_Expr.Get_Value_Memtyp (Res); end; when others => |