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| author | Tristan Gingold <tgingold@free.fr> | 2022-09-16 19:55:00 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-09-16 19:55:00 +0200 |
| commit | 2a51f0c5c65d5d71c5abbd0631a0ec5660678520 (patch) | |
| tree | a3f077806dced3a7106bf990f589184fbde30d62 /src/simul | |
| parent | 7f411fd357bc9a17dc3d0593b86f4b8412a94632 (diff) | |
| download | ghdl-2a51f0c5c65d5d71c5abbd0631a0ec5660678520.tar.gz ghdl-2a51f0c5c65d5d71c5abbd0631a0ec5660678520.tar.bz2 ghdl-2a51f0c5c65d5d71c5abbd0631a0ec5660678520.zip | |
synth: preliminary work to factorize code
Diffstat (limited to 'src/simul')
| -rw-r--r-- | src/simul/simul-vhdl_elab.adb | 18 |
1 files changed, 5 insertions, 13 deletions
diff --git a/src/simul/simul-vhdl_elab.adb b/src/simul/simul-vhdl_elab.adb index 01cfc6b9a..89cf9cf17 100644 --- a/src/simul/simul-vhdl_elab.adb +++ b/src/simul/simul-vhdl_elab.adb @@ -423,7 +423,6 @@ package body Simul.Vhdl_Elab is Base : Signal_Index_Type; Typ : Type_Acc; Off : Value_Offsets; - Dyn : Dyn_Name; begin Mark_Expr_Pool (Marker); @@ -432,8 +431,7 @@ package body Simul.Vhdl_Elab is while Is_Valid (It) loop Sig := Get_Element (It); exit when Sig = Null_Node; - Synth_Assignment_Prefix (Inst, Sig, Base_Vt, Typ, Off, Dyn); - pragma Assert (Dyn = No_Dyn_Name); + Synth_Assignment_Prefix (Inst, Sig, Base_Vt, Typ, Off); Base := Base_Vt.Val.S; Typ := Unshare (Typ, Global_Pool'Access); @@ -457,7 +455,6 @@ package body Simul.Vhdl_Elab is Base : Signal_Index_Type; Typ : Type_Acc; Off : Value_Offsets; - Dyn : Dyn_Name; begin Mark_Expr_Pool (Marker); @@ -465,8 +462,7 @@ package body Simul.Vhdl_Elab is while Is_Valid (It) loop Sig := Get_Element (It); exit when Sig = Null_Node; - Synth_Assignment_Prefix (Inst, Sig, Base_Vt, Typ, Off, Dyn); - pragma Assert (Dyn = No_Dyn_Name); + Synth_Assignment_Prefix (Inst, Sig, Base_Vt, Typ, Off); Base := Base_Vt.Val.S; Typ := Unshare (Typ, Global_Pool'Access); @@ -580,7 +576,6 @@ package body Simul.Vhdl_Elab is Actual_Sig : Signal_Index_Type; Typ : Type_Acc; Off : Value_Offsets; - Dyn : Dyn_Name; Conn : Connect_Entry; List : Iir_List; Formal_Ep, Actual_Ep : Connect_Endpoint; @@ -597,15 +592,13 @@ package body Simul.Vhdl_Elab is Formal := Inter; end if; Synth_Assignment_Prefix - (Port_Inst, Formal, Formal_Base, Typ, Off, Dyn); - pragma Assert (Dyn = No_Dyn_Name); + (Port_Inst, Formal, Formal_Base, Typ, Off); Typ := Unshare (Typ, Global_Pool'Access); Formal_Sig := Formal_Base.Val.S; Formal_Ep := (Formal_Sig, Off, Typ); Synth_Assignment_Prefix - (Assoc_Inst, Get_Actual (Assoc), Actual_Base, Typ, Off, Dyn); - pragma Assert (Dyn = No_Dyn_Name); + (Assoc_Inst, Get_Actual (Assoc), Actual_Base, Typ, Off); Typ := Unshare (Typ, Global_Pool'Access); Actual_Sig := Actual_Base.Val.S; Actual_Ep := (Actual_Sig, Off, Typ); @@ -666,8 +659,7 @@ package body Simul.Vhdl_Elab is when Iir_Kind_Association_Element_By_Expression => Inter := Get_Association_Interface (Assoc, Assoc_Inter); Synth_Assignment_Prefix - (Port_Inst, Inter, Formal_Base, Typ, Off, Dyn); - pragma Assert (Dyn = No_Dyn_Name); + (Port_Inst, Inter, Formal_Base, Typ, Off); Formal_Sig := Formal_Base.Val.S; Formal_Ep := (Formal_Sig, Off, Typ); |