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| author | Tristan Gingold <tgingold@free.fr> | 2022-09-18 08:57:27 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-09-18 08:57:27 +0200 |
| commit | f0900d17ff6ac00d3653e7aea5af166b603b155a (patch) | |
| tree | b7631cf8c8115cf8d1151f5c714c25a785c46efd /src/simul | |
| parent | 712c08710de22ecbcbf42527ef516160591a1000 (diff) | |
| download | ghdl-f0900d17ff6ac00d3653e7aea5af166b603b155a.tar.gz ghdl-f0900d17ff6ac00d3653e7aea5af166b603b155a.tar.bz2 ghdl-f0900d17ff6ac00d3653e7aea5af166b603b155a.zip | |
synth-vhdl_stmts: minor renaming
Diffstat (limited to 'src/simul')
| -rw-r--r-- | src/simul/simul-vhdl_simul.adb | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/simul/simul-vhdl_simul.adb b/src/simul/simul-vhdl_simul.adb index b5f14a067..4a8ef443f 100644 --- a/src/simul/simul-vhdl_simul.adb +++ b/src/simul/simul-vhdl_simul.adb @@ -758,7 +758,7 @@ package body Simul.Vhdl_Simul is pragma Assert (Obj = Null_Node); Sub_Inst := Synth_Subprogram_Call_Instance (Inst, Imp, Imp); - Synth_Subprogram_Association + Synth_Subprogram_Associations (Sub_Inst, Inst, Inter_Chain, Assoc_Chain); Synth.Vhdl_Static_Proc.Synth_Static_Procedure @@ -791,7 +791,7 @@ package body Simul.Vhdl_Simul is -- Note: in fact the uninstantiated scope is the instantiated -- one! Set_Uninstantiated_Scope (Sub_Inst, Imp); - Synth_Subprogram_Association + Synth_Subprogram_Associations (Sub_Inst, Inst, Inter_Chain, Assoc_Chain); Process.Instance := Sub_Inst; |