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* simul: improve support of PSL endpointsTristan Gingold2023-02-081-8/+1
* simul: handle signal assignment to procedure individual associationsTristan Gingold2023-02-081-8/+19
* synth: use same layout for records in memory as translateTristan Gingold2023-02-081-1/+1
* simul: refactoring, expose more subprogramsTristan Gingold2023-02-043-35/+47
* elab-debugger: also pass top instance on break_timeTristan Gingold2023-01-311-1/+1
* ghdlsimul: extract simul-main from simul-vhdl_simulTristan Gingold2023-01-315-108/+182
* simul-vhdl_elab: fix computation of nbr of sourcesTristan Gingold2023-01-301-2/+7
* simul: use same packing order for nets and for values.Tristan Gingold2023-01-302-27/+25
* simul: improve info sig and info timeTristan Gingold2023-01-301-52/+78
* synth: create sub-instace for processesTristan Gingold2023-01-201-0/+1
* simul: handle PSL endpointsTristan Gingold2023-01-182-10/+29
* simul: fix last_value for post vhdl 87Tristan Gingold2023-01-182-103/+145
* simul: disable --trace-signalsTristan Gingold2023-01-151-0/+4
* synth: improve error propagation on slicesTristan Gingold2023-01-141-1/+4
* synth: handle protected functions in conversion functionsTristan Gingold2023-01-121-1/+2
* simul: handle PSL abortsTristan Gingold2023-01-122-0/+67
* simul: fix handling of drivers/sensitivity within processesTristan Gingold2023-01-122-21/+24
* simul: avoid a crash after an error in a conditionTristan Gingold2023-01-111-1/+6
* synth: improve support of PSL endpointsTristan Gingold2023-01-111-1/+2
* simul: allow function calls in signal association by valueTristan Gingold2023-01-111-0/+2
* simul: handle psl assume directivesTristan Gingold2023-01-111-0/+2
* simul: add sensitivity for psl processesTristan Gingold2023-01-111-4/+7
* simul: improve assertion messages for pslTristan Gingold2023-01-111-5/+15
* simul: add debug command 'run -s'Tristan Gingold2023-01-113-8/+18
* simul: handle array element resolutionTristan Gingold2023-01-111-1/+6
* simul: improve debugger outputTristan Gingold2023-01-111-5/+5
* simul: enable all debug features during elaborationTristan Gingold2023-01-102-5/+3
* synth: handle indexes in arrays conversionTristan Gingold2023-01-101-2/+2
* simul: handle inertial assignmentsTristan Gingold2023-01-101-2/+14
* synth-vhdl_aggr: optimize common aggregateTristan Gingold2023-01-101-6/+8
* synth: always create shared variablesTristan Gingold2023-01-091-21/+2
* simul: set assertion hook before elaborationTristan Gingold2023-01-091-3/+3
* simul-vhdl_simul: fix effective value writesTristan Gingold2023-01-091-1/+20
* simul: handle function calls in sensitivity compute.Tristan Gingold2023-01-091-0/+6
* simul: improve error recovery during elaborationTristan Gingold2023-01-091-3/+12
* simul: handle PSL coverTristan Gingold2023-01-092-3/+7
* simul: handle force/release signal assignmentsTristan Gingold2023-01-031-0/+174
* synth: introduce type_array_unboundedTristan Gingold2023-01-033-0/+4
* simul: skip psl default clock in declarationsTristan Gingold2023-01-031-0/+1
* synth: fix to_string for characterTristan Gingold2023-01-021-0/+3
* synth: elaborate case generate statementsTristan Gingold2023-01-011-1/+2
* simul: handle nested packagesTristan Gingold2023-01-011-1/+5
* synth: add statement in context, adjust path/instance name attributesTristan Gingold2022-12-311-1/+1
* simul: handle driving and driving_value attributesTristan Gingold2022-12-261-6/+39
* simul: handle transaction attributeTristan Gingold2022-12-262-3/+13
* simul: handle aggregate is guarded signal assignment targetTristan Gingold2022-12-261-7/+29
* vhdl-canon: handle unaffectedTristan Gingold2022-12-261-0/+5
* synth: add value_sig_val to handle individual signal associationsTristan Gingold2022-12-261-28/+166
* vhdl-sem_inst: add instantiate_interface_package_declarationTristan Gingold2022-12-181-0/+4
* vhdl: fix some compiler warningsTristan Gingold2022-11-082-4/+0
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