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| author | Tristan Gingold <tgingold@free.fr> | 2022-09-26 07:53:37 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-09-26 07:53:37 +0200 |
| commit | 0253646671c6000da87d12bebb2166284273ae04 (patch) | |
| tree | 45bfefa0b44858efa7378d8567650d97e3ea8153 /src/simul | |
| parent | 476236deae896de421daab68890e2e2473caf13d (diff) | |
| download | ghdl-0253646671c6000da87d12bebb2166284273ae04.tar.gz ghdl-0253646671c6000da87d12bebb2166284273ae04.tar.bz2 ghdl-0253646671c6000da87d12bebb2166284273ae04.zip | |
synth: handle attributes in configurations
Diffstat (limited to 'src/simul')
| -rw-r--r-- | src/simul/simul-vhdl_elab.adb | 4 | ||||
| -rw-r--r-- | src/simul/simul-vhdl_simul.adb | 2 |
2 files changed, 4 insertions, 2 deletions
diff --git a/src/simul/simul-vhdl_elab.adb b/src/simul/simul-vhdl_elab.adb index 0fd99b551..ac2bc25c1 100644 --- a/src/simul/simul-vhdl_elab.adb +++ b/src/simul/simul-vhdl_elab.adb @@ -912,8 +912,10 @@ package body Simul.Vhdl_Elab is when Iir_Kind_Package_Declaration => Gather_Processes_Decls (Inst, Get_Declaration_Chain (N)); + when Iir_Kind_Configuration_Declaration => + null; when others => - Vhdl.Errors.Error_Kind ("gater_processes_1", N); + Vhdl.Errors.Error_Kind ("gather_processes_1", N); end case; pragma Assert (Areapools.Is_Empty (Expr_Pool)); diff --git a/src/simul/simul-vhdl_simul.adb b/src/simul/simul-vhdl_simul.adb index f7a51b822..e5ca86a53 100644 --- a/src/simul/simul-vhdl_simul.adb +++ b/src/simul/simul-vhdl_simul.adb @@ -2581,8 +2581,8 @@ package body Simul.Vhdl_Simul is Grt.Errors.Fatal_Error; end if; - pragma Assert (Dst_Val.Typ.Wkind = Wkind_Sim); Convert_Type_Width (Dst_Val.Typ); + pragma Assert (Dst_Val.Typ.Wkind = Wkind_Sim); Dst := Synth.Vhdl_Expr.Get_Value_Memtyp (Dst_Val); case Conv.Mode is |