simul: handle quiet attribute

2 files changed, 72 insertions, 7 deletions

diff --git a/src/simul/simul-vhdl_elab.adb b/src/simul/simul-vhdl_elab.adb
index 7e37c28d5..734ff2b2e 100644
--- a/src/simul/simul-vhdl_elab.adb
+++ b/src/simul/simul-vhdl_elab.adb
@@ -248,6 +248,24 @@ package body Simul.Vhdl_Elab is
       Val.Val.T := Terminal_Table.Last;
    end Gather_Terminal;
 
+   function Compute_Attribute_Time (Inst : Synth_Instance_Acc; Attr : Node)
+                                   return Std_Time
+   is
+      Param : constant Node := Get_Parameter (Attr);
+      Marker : Mark_Type;
+      Val : Valtyp;
+      Res : Std_Time;
+   begin
+      if Param = Null_Node then
+         return 0;
+      end if;
+      Mark_Expr_Pool (Marker);
+      Val := Synth.Vhdl_Expr.Synth_Expression (Inst, Param);
+      Res := Std_Time (Read_Discrete (Val));
+      Release_Expr_Pool (Marker);
+      return Res;
+   end Compute_Attribute_Time;
+
    procedure Gather_Processes_Decl (Inst : Synth_Instance_Acc; Decl : Node) is
    begin
       case Get_Kind (Decl) is
@@ -319,6 +337,17 @@ package body Simul.Vhdl_Elab is
          when Iir_Kind_Above_Attribute =>
             Gather_Signal ((Mode_Above, Decl, Inst, null, null, null,
                             No_Sensitivity_Index, No_Signal_Index));
+         when Iir_Kind_Quiet_Attribute =>
+            declare
+               T : Std_Time;
+               Pfx : Sub_Signal_Type;
+            begin
+               T := Compute_Attribute_Time (Inst, Decl);
+               Pfx := Compute_Sub_Signal (Inst, Get_Prefix (Decl));
+               Gather_Signal ((Mode_Quiet, Decl, Inst, null, null, null,
+                               No_Sensitivity_Index, No_Signal_Index,
+                               T, Pfx));
+            end;
          when Iir_Kind_Object_Alias_Declaration =>
             --  In case it aliases a signal.
             declare
diff --git a/src/simul/simul-vhdl_simul.adb b/src/simul/simul-vhdl_simul.adb
index b86a4a7d5..72d5be782 100644
--- a/src/simul/simul-vhdl_simul.adb
+++ b/src/simul/simul-vhdl_simul.adb
@@ -2436,6 +2436,32 @@ package body Simul.Vhdl_Simul is
       end loop;
    end Create_Guard_Signal;
 
+   procedure Register_Prefix (Typ : Type_Acc; Sig : Memory_Ptr) is
+   begin
+      case Typ.Kind is
+         when Type_Scalars =>
+            Grt.Signals.Ghdl_Signal_Attribute_Register_Prefix (Read_Sig (Sig));
+         when Type_Vector
+           | Type_Array =>
+            declare
+               Len : constant Uns32 := Typ.Abound.Len;
+            begin
+               for I in 1 .. Len loop
+                  Register_Prefix
+                    (Typ.Arr_El, Sig_Index (Sig, (Len - I) * Typ.Arr_El.W));
+               end loop;
+            end;
+         when Type_Record =>
+            for I in Typ.Rec.E'Range loop
+               Register_Prefix
+                 (Typ.Rec.E (I).Typ,
+                  Sig_Index (Sig, Typ.Rec.E (I).Offs.Net_Off));
+            end loop;
+         when others =>
+            raise Internal_Error;
+      end case;
+   end Register_Prefix;
+
    function Alloc_Signal_Memory (Vtype : Type_Acc) return Memory_Ptr
    is
       function To_Memory_Ptr is new Ada.Unchecked_Conversion
@@ -2447,15 +2473,31 @@ package body Simul.Vhdl_Simul is
       return To_Memory_Ptr (M);
    end Alloc_Signal_Memory;
 
+   function To_Memory_Ptr (S : Sub_Signal_Type) return Memory_Ptr is
+   begin
+      return Sig_Index (Signals_Table.Table (S.Base).Sig, S.Offs.Net_Off);
+   end To_Memory_Ptr;
+
+   function To_Memtyp (S : Sub_Signal_Type) return Memtyp is
+   begin
+      return (S.Typ, To_Memory_Ptr (S));
+   end To_Memtyp;
+
    procedure Create_Signal (Idx : Signal_Index_Type)
    is
       E : Signal_Entry renames Signals_Table.Table (Idx);
+      S : Ghdl_Signal_Ptr;
    begin
       E.Sig := Alloc_Signal_Memory (E.Typ);
       case E.Kind is
          when Mode_Guard =>
             Create_Guard_Signal (Idx);
-         when Mode_Stable | Mode_Quiet | Mode_Transaction =>
+         when Mode_Quiet =>
+            S := Grt.Signals.Ghdl_Create_Quiet_Signal
+              (To_Ghdl_Value_Ptr (To_Address (E.Val)), E.Time);
+            Write_Sig (E.Sig, S);
+            Register_Prefix (E.Pfx.Typ, To_Memory_Ptr (E.Pfx));
+         when Mode_Stable | Mode_Transaction =>
             -- Create_Implicit_Signal
             --  (E.Sig, E.Val, E.Time, E.Prefix, E.Kind);
             raise Internal_Error;
@@ -2553,12 +2595,6 @@ package body Simul.Vhdl_Simul is
 
    type Connect_Mode is (Connect_Source, Connect_Effective);
 
-   function To_Memtyp (Ep : Sub_Signal_Type) return Memtyp is
-   begin
-      return (Ep.Typ,
-              Sig_Index (Signals_Table.Table (Ep.Base).Sig, Ep.Offs.Net_Off));
-   end To_Memtyp;
-
    -- Add a driving value PORT to signal SIG, ie: PORT is a source for SIG.
    -- As a side effect, this connect the signal SIG with the port PORT.
    -- PORT is the formal, while SIG is the actual.