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| author | Tristan Gingold <tgingold@free.fr> | 2022-09-12 05:12:37 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-09-12 05:15:16 +0200 |
| commit | b1c8c9a1e6a32ed390a2e73c928ca15762ec20b2 (patch) | |
| tree | df8b1054ef0b69fd114a97526ff1ee6f491731d6 /src/simul | |
| parent | 904abc55c0821f85151a8328904f5621e60c8f02 (diff) | |
| download | ghdl-b1c8c9a1e6a32ed390a2e73c928ca15762ec20b2.tar.gz ghdl-b1c8c9a1e6a32ed390a2e73c928ca15762ec20b2.tar.bz2 ghdl-b1c8c9a1e6a32ed390a2e73c928ca15762ec20b2.zip | |
simul: do not consider signal parameters as dynamic values
Diffstat (limited to 'src/simul')
| -rw-r--r-- | src/simul/simul-vhdl_simul.adb | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/simul/simul-vhdl_simul.adb b/src/simul/simul-vhdl_simul.adb index 344302aa3..646496a66 100644 --- a/src/simul/simul-vhdl_simul.adb +++ b/src/simul/simul-vhdl_simul.adb @@ -3043,6 +3043,7 @@ package body Simul.Vhdl_Simul is pragma Assert (Areapools.Is_Empty (Process_Pool)); Synth.Flags.Severity_Level := Grt.Options.Severity_Level; + Synth.Flags.Flag_Simulation := True; if Flag_Interractive then Elab.Debugger.Debug_Elab (Vhdl_Elab.Top_Instance); |