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| author | Tristan Gingold <tgingold@free.fr> | 2022-08-25 18:35:08 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-08-25 18:35:08 +0200 |
| commit | f66dfc0dacbb9994f01c45af04cf9b2a505d6f78 (patch) | |
| tree | c37524fac043eccad9d165a35c2b40da8043ad74 /src/simul | |
| parent | 71973b9b2a69b0d59e829629fa5750db997c00f1 (diff) | |
| download | ghdl-f66dfc0dacbb9994f01c45af04cf9b2a505d6f78.tar.gz ghdl-f66dfc0dacbb9994f01c45af04cf9b2a505d6f78.tar.bz2 ghdl-f66dfc0dacbb9994f01c45af04cf9b2a505d6f78.zip | |
simul: handle connections of records
Diffstat (limited to 'src/simul')
| -rw-r--r-- | src/simul/simul-vhdl_simul.adb | 19 |
1 files changed, 18 insertions, 1 deletions
diff --git a/src/simul/simul-vhdl_simul.adb b/src/simul/simul-vhdl_simul.adb index fbd649142..321c30130 100644 --- a/src/simul/simul-vhdl_simul.adb +++ b/src/simul/simul-vhdl_simul.adb @@ -2260,9 +2260,26 @@ package body Simul.Vhdl_Simul is end loop; end; return; + when Type_Record => + for I in Dst.Typ.Rec.E'Range loop + declare + E : Rec_El_Type renames Dst.Typ.Rec.E (I); + begin + Connect ((Dst.Sig, + (Dst.Offs.Net_Off + E.Offs.Net_Off, + Dst.Offs.Mem_Off + E.Offs.Mem_Off), + E.Typ), + (Src.Sig, + (Src.Offs.Net_Off + E.Offs.Net_Off, + Src.Offs.Mem_Off + E.Offs.Mem_Off), + Src.Typ.Rec.E (I).Typ), + Mode); + end; + end loop; when Type_Logic | Type_Bit - | Type_Discrete => + | Type_Discrete + | Type_Float => declare S, D : Ghdl_Signal_Ptr; begin |