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| * | | | Cleanup testsEddie Hung2020-02-272-1/+1
| * | | | Update bug1630.ys to use -lut 4 instead of lut fileEddie Hung2020-02-271-1/+1
| * | | | Fix tests/arch/xilinx/fsm.ys to count flops onlyEddie Hung2020-02-271-9/+3
| * | | | Update simple_abc9 testsEddie Hung2020-02-273-5/+8
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* / | | ast: fixes #1710; do not generate RTLIL for unreachable ternaryEddie Hung2020-02-271-0/+30
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* | | Merge pull request #1703 from YosysHQ/eddie/specify_improveEddie Hung2020-02-212-3/+47
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| * | | clean: ignore specify-s inside cells when determining whether to keepEddie Hung2020-02-191-1/+20
| * | | verilog: ignore ranges too without -specifyEddie Hung2020-02-131-0/+7
| * | | verilog: improve specify support when not in -specify modeEddie Hung2020-02-132-3/+1
| * | | verilog: ignore '&&&' when not in -specify modeEddie Hung2020-02-131-0/+6
| * | | specify: system timing checks to accept min:typ:max tripleEddie Hung2020-02-131-0/+7
| * | | verilog: fix $specify3 checkEddie Hung2020-02-131-0/+7
* | | | Merge pull request #1642 from jjj11x/jjj11x/sv-enumClaire Wolf2020-02-204-1/+68
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| * | | | add attributes for enumerated values in ilangJeff Wang2020-02-172-3/+3
| * | | | scoped enum testsJeff Wang2020-01-161-1/+13
| * | | | enum in package testJeff Wang2020-01-161-0/+3
| * | | | simple enum testJeff Wang2020-01-162-0/+52
* | | | | tests/aiger: Add missing .gitignoreMarcin Kościelnicki2020-02-151-0/+2
* | | | | Merge pull request #1701 from nakengelhardt/rpc-testMiodrag Milanović2020-02-143-7/+7
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| * | | | | make rpc frontend unix socket test less fragileN. Engelhardt2020-02-133-7/+7
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* | | | | Fine tune #1699 testsEddie Hung2020-02-131-14/+14
* | | | | iopadmap: move \init attributes from outpad output to its inputEddie Hung2020-02-131-0/+37
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* | | | Merge pull request #1679 from thasti/delay-parsingN. Engelhardt2020-02-131-0/+5
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| * | | | add testcase for #1614Stefan Biereigel2020-02-031-0/+5
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* | | | Merge pull request #1670 from rodrigomelo9/masterEddie Hung2020-02-104-0/+137
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| * | | | Added 'set -e' into tests/memfile/run-test.shRodrigo Alejandro Melo2020-02-061-0/+20
| * | | | Merge branch 'master' into masterRodrigo A. Melo2020-02-034-4/+84
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| * \ \ \ \ Merge branch 'master' of https://github.com/YosysHQ/yosysRodrigo Alejandro Melo2020-02-032-0/+136
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| * | | | | | Removed 'synth' into tests/memfile/run-test.shRodrigo Alejandro Melo2020-02-021-8/+8
| * | | | | | Added content1.dat into tests/memfileRodrigo Alejandro Melo2020-02-022-21/+81
| * | | | | | Added tests/memfile to 'make test' with an extra testcaseRodrigo Alejandro Melo2020-02-011-16/+10
| * | | | | | Added a test for the Memory Content File inclusion using $readmembRodrigo Alejandro Melo2020-02-013-0/+63
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* | | | | | xilinx: Add support for LUT RAM on LUT4-based devices.Marcin Kościelnicki2020-02-071-0/+20
* | | | | | xilinx: Initial support for LUT4 devices.Marcin Kościelnicki2020-02-073-1/+83
* | | | | | shiftx2mux: fix select out of boundsEddie Hung2020-02-052-1/+12
* | | | | | Merge pull request #1576 from YosysHQ/eddie/opt_merge_initEddie Hung2020-02-051-0/+49
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| * \ \ \ \ \ Merge remote-tracking branch 'origin/master' into eddie/opt_merge_initEddie Hung2020-01-2874-149/+1770
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| * | | | | | | Add testcaseEddie Hung2019-12-131-0/+49
* | | | | | | | Merge pull request #1650 from YosysHQ/eddie/shiftx2muxEddie Hung2020-02-053-5/+115
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| * \ \ \ \ \ \ \ Merge remote-tracking branch 'origin/master' into eddie/shiftx2muxEddie Hung2020-02-0517-30/+474
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| * | | | | | | | | Update tests with reduced areaEddie Hung2020-01-212-6/+6
| * | | | | | | | | Move from +/shiftx2mux.v into +/techmap.v; cleanupEddie Hung2020-01-211-4/+4
| * | | | | | | | | New techmap +/shiftx2mux.v which decomposes LSB first; better for ABCEddie Hung2020-01-211-0/+110
* | | | | | | | | | abc9_ops: -reintegrate to use derived_type for box_portsEddie Hung2020-02-051-1/+21
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* | | | | | | | | Merge pull request #1638 from YosysHQ/eddie/fix1631Eddie Hung2020-02-051-0/+66
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| * | | | | | | | More rigorous testEddie Hung2020-01-161-7/+34
| * | | | | | | | clk2fflogic: work for bit-level $_DFF_* and $_DFFSR_*Eddie Hung2020-01-151-0/+39
* | | | | | | | | Add opt_lut_ins pass. (#1673)Marcelina Kościelnicka2020-02-034-4/+84
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* | | | | | | | sv: More tests for wildcard port connectionsDavid Shah2020-02-021-0/+57
* | | | | | | | hierarchy: Correct handling of wildcard port connections with default valuesDavid Shah2020-02-021-0/+11
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