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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-16 15:25:49 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-21 15:19:41 -0800 |
| commit | 7977574995baa2cdba1401233179f9f84fe96a3a (patch) | |
| tree | 1649fe008d42e3b9be19aec510b6266da8749c32 /tests | |
| parent | f165a748244b022b215631ade2c8a5e0139cec09 (diff) | |
| download | yosys-7977574995baa2cdba1401233179f9f84fe96a3a.tar.gz yosys-7977574995baa2cdba1401233179f9f84fe96a3a.tar.bz2 yosys-7977574995baa2cdba1401233179f9f84fe96a3a.zip | |
New techmap +/shiftx2mux.v which decomposes LSB first; better for ABC
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/techmap/shiftx2mux.ys | 110 |
1 files changed, 110 insertions, 0 deletions
diff --git a/tests/techmap/shiftx2mux.ys b/tests/techmap/shiftx2mux.ys new file mode 100644 index 000000000..acdd54e9e --- /dev/null +++ b/tests/techmap/shiftx2mux.ys @@ -0,0 +1,110 @@ +read_verilog <<EOT +module sc1 (i1 , + i2 , + i3 , + i4 , + i5 , + i6 , + i7 , + i8 , + i9 , + i10, + i11, + i12, + i13, + i14, + i15, + binary_out, + encoder_in, + enable +); + +input [3:0] i1 ; +input [3:0] i2 ; +input [3:0] i3 ; +input [3:0] i4 ; +input [3:0] i5 ; +input [3:0] i6 ; +input [3:0] i7 ; +input [3:0] i8 ; +input [3:0] i9 ; +input [3:0] i10 ; +input [3:0] i11 ; +input [3:0] i12 ; +input [3:0] i13 ; +input [3:0] i14 ; +input [3:0] i15 ; + +output reg [3:0] binary_out ; + +input [3:0] encoder_in ; +input enable ; + + + +always @ (*) +begin + binary_out = 0; + if (enable) begin + case (encoder_in) + 4'h1 : binary_out = i1; + 4'h2 : binary_out = i2; + 4'h3 : binary_out = i3; + 4'h4 : binary_out = i4; + 4'h5 : binary_out = i5; + 4'h6 : binary_out = i6; + 4'h7 : binary_out = i7; + 4'h8 : binary_out = i8; + 4'h9 : binary_out = i9; + 4'ha : binary_out = i10; + 4'hb : binary_out = i11;/* + 4'hc : binary_out = i12; + 4'hd : binary_out = i13; + 4'he : binary_out = i14; + 4'hf : binary_out = i15;*/ + endcase + end +end +endmodule +EOT + +proc +pmux2shiftx +design -save gold + + +design -load gold +techmap +abc -lut 6 +select -assert-min 17 t:$lut + + +design -load gold +techmap -map +/shiftx2mux.v -map +/techmap.v +abc -lut 6 +select -assert-count 16 t:$lut + +design -stash gate +design -import gold -as gold +design -import gate -as gate +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports miter + + +design -load gold +techmap +abc9 -lut 6 +select -assert-min 17 t:$lut + + +design -load gold +techmap -map +/shiftx2mux.v -map +/techmap.v +abc9 -lut 6 +select -assert-count 16 t:$lut + +design -stash gate +design -import gold -as gold +design -import gate -as gate +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports miter + |