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Author
Age
Files
Lines
*
Add initial support for both MAX10 and Cyclone IV (E|GX) FPGAs
dh73
2017-04-05
8
-0
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+968
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Merge branch 'master' of github.com:cliffordwolf/yosys
Clifford Wolf
2017-02-25
1
-3
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+4
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Merge https://github.com/cliffordwolf/yosys
Andrew Zonenberg
2017-02-14
1
-2
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+0
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*
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Merge https://github.com/cliffordwolf/yosys
Andrew Zonenberg
2017-02-08
1
-0
/
+8
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greenpak4: Added POUT to GP_COUNTx cells
Andrew Zonenberg
2017-01-01
1
-3
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+4
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Add $live and $fair cell types, add support for s_eventually keyword
Clifford Wolf
2017-02-25
1
-0
/
+16
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*
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Fix double-call of log_pop() in synth_greenpak4
Clifford Wolf
2017-02-14
1
-2
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+0
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*
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Add $cover cell type and SVA cover() support
Clifford Wolf
2017-02-04
1
-0
/
+8
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greenpak4: Added INT pin to GP_SPI
Andrew Zonenberg
2016-12-21
1
-1
/
+3
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greenpak4: removed unused MISO pin from GP_SPI
Andrew Zonenberg
2016-12-21
1
-1
/
+0
*
greenpak4: Removed SPI_BUFFER parameter
Andrew Zonenberg
2016-12-20
1
-1
/
+0
*
greenpak4: replaced MOSI/MISO with single one-way SDAT pin
Andrew Zonenberg
2016-12-20
1
-2
/
+1
*
greenpak4: Changed port names on GP_SPI for clarity
Andrew Zonenberg
2016-12-20
1
-4
/
+4
*
greenpak4: Initial implementation of GP_SPI cell
Andrew Zonenberg
2016-12-20
1
-0
/
+27
*
greenpak4: Updated GP_DCMP cell model
Andrew Zonenberg
2016-12-17
1
-2
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+20
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greenpak: Fixes to GP_DCMP* blocks. Added GP_CLKBUF.
Andrew Zonenberg
2016-12-16
1
-5
/
+10
*
greenpak4: Initial version of GP_DCMP skeleton (not yet usable). Changed inte...
Andrew Zonenberg
2016-12-15
1
-5
/
+24
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greenpak4: More fixups of GP_DCMPx cells
Andrew Zonenberg
2016-12-15
1
-9
/
+3
*
greenpak4: And another typo :(
Andrew Zonenberg
2016-12-15
1
-1
/
+1
*
greenpak4: Fixed another typo
Andrew Zonenberg
2016-12-15
1
-1
/
+1
*
greenpak4: Fixed typo
Andrew Zonenberg
2016-12-15
1
-1
/
+1
*
greenpak4: Cleaned up trailing spaces in cells_sim
Andrew Zonenberg
2016-12-14
1
-60
/
+60
*
greenpak4: Added GP_DCMPREF / GP_DCMPMUX
Andrew Zonenberg
2016-12-14
1
-0
/
+23
*
Added GP_PWRDET block, BANDWIDTH_KHZ parameter to GP_ABUF
Andrew Zonenberg
2016-12-11
1
-1
/
+9
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greenpak4: Added support for inferred input/output inverters on latches
Andrew Zonenberg
2016-12-10
1
-4
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+17
*
greenpak4: Can now techmap inferred D latches (without set/reset or output in...
Andrew Zonenberg
2016-12-10
3
-0
/
+17
*
greenpak4: Inverted D latch cells now have nQ instead of Q as output port nam...
Andrew Zonenberg
2016-12-10
1
-15
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+15
*
Added GP_DLATCH and GP_DLATCHI
Andrew Zonenberg
2016-12-05
1
-0
/
+18
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Initial implementation of techlib support for GreenPAK latches. Instantiation...
Andrew Zonenberg
2016-12-05
2
-0
/
+120
*
Updated help text for synth_greenpak4
Andrew Zonenberg
2016-12-05
1
-0
/
+2
*
Indenting fixes in gowin sim cell lib
Clifford Wolf
2016-11-08
1
-20
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+28
*
Added hex constant support to write_verilog
Clifford Wolf
2016-11-03
1
-1
/
+1
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iCE40 flow is not experimental anymore
Clifford Wolf
2016-11-01
1
-1
/
+1
*
Added initial version of "synth_gowin"
Clifford Wolf
2016-11-01
4
-0
/
+266
*
Fixed typo in last commit
Andrew Zonenberg
2016-10-18
1
-1
/
+1
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greenpak4: Added GP_PGEN cell definition
Andrew Zonenberg
2016-10-18
1
-0
/
+21
*
Added GLITCH_FILTER parameter to GP_DELAY
Andrew Zonenberg
2016-10-18
1
-3
/
+2
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greenpak4: added model for GP_EDGEDET block
Andrew Zonenberg
2016-10-18
1
-0
/
+10
*
greenpak4: Changed parameters for GP_SYSRESET
Andrew Zonenberg
2016-10-16
1
-1
/
+2
*
Added $anyseq cell type
Clifford Wolf
2016-10-14
1
-0
/
+12
*
Added $global_clock verilog syntax support for creating $ff cells
Clifford Wolf
2016-10-14
2
-2
/
+23
*
Added $ff and $_FF_ cell types
Clifford Wolf
2016-10-12
2
-1
/
+14
*
Added "prep -nokeepdc"
Clifford Wolf
2016-09-30
1
-4
/
+12
*
Added "prep -nomem"
Clifford Wolf
2016-08-30
1
-6
/
+16
*
Removed $aconst cell type
Clifford Wolf
2016-08-30
1
-12
/
+0
*
Removed $predict again
Clifford Wolf
2016-08-28
1
-8
/
+0
*
Added "wreduce -memx"
Clifford Wolf
2016-08-20
1
-2
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+6
*
Added memory_memx pass, "memory -memx", and "prep -memx"
Clifford Wolf
2016-08-19
1
-2
/
+17
*
Added greenpak4_dffinv
Clifford Wolf
2016-08-15
3
-0
/
+199
*
greenpak4: Changed name of inverted output ports for consistency
Andrew Zonenberg
2016-08-14
2
-19
/
+19
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