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| author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-12-15 07:16:26 +0800 |
|---|---|---|
| committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-12-15 07:16:26 +0800 |
| commit | ea787e6be3d8559dbf9994d73283d9a234273fe9 (patch) | |
| tree | 29bdcd9a551ae1637bda803df382f1bef417872b /techlibs | |
| parent | 58da621ac3892bda42e31faa6ac4f02bc9cf3f87 (diff) | |
| download | yosys-ea787e6be3d8559dbf9994d73283d9a234273fe9.tar.gz yosys-ea787e6be3d8559dbf9994d73283d9a234273fe9.tar.bz2 yosys-ea787e6be3d8559dbf9994d73283d9a234273fe9.zip | |
greenpak4: Fixed another typo
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/greenpak4/cells_sim.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index d5a06a453..65f4a6f70 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -137,7 +137,7 @@ module GP_DCMPREF(output OUT); wire[7:0] OUT = REF_VAL; endmodule -module GP_DCMPMUX(input SEL, input IN0, input IN1, input IN2, input IN3, output OUT) +module GP_DCMPMUX(input SEL, input IN0, input IN1, input IN2, input IN3, output OUT); wire[1:0] SEL; wire[7:0] IN0; wire[7:0] IN1; |