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| author | Clifford Wolf <clifford@clifford.at> | 2017-02-04 14:14:26 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-02-04 14:14:26 +0100 |
| commit | 3928482a3c4fb71b8e6ccdcb362c030eef34a479 (patch) | |
| tree | 482ea8a72c3bae5bafc377136d10426898cb8ac5 /techlibs | |
| parent | 911c44d164e04026bd3a3a2eb1bf0c5d9cca5c19 (diff) | |
| download | yosys-3928482a3c4fb71b8e6ccdcb362c030eef34a479.tar.gz yosys-3928482a3c4fb71b8e6ccdcb362c030eef34a479.tar.bz2 yosys-3928482a3c4fb71b8e6ccdcb362c030eef34a479.zip | |
Add $cover cell type and SVA cover() support
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/common/simlib.v | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index 2c4db1ac6..d0abd3b34 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -1305,6 +1305,14 @@ endmodule // -------------------------------------------------------- +module \$cover (A, EN); + +input A, EN; + +endmodule + +// -------------------------------------------------------- + module \$initstate (Y); output reg Y = 1; |