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| author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-12-20 12:34:56 +0800 |
|---|---|---|
| committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-12-20 12:34:56 +0800 |
| commit | 073e8df9f1ca88ae30f5c61f7a620b02210e1747 (patch) | |
| tree | ca8bf18b2457ff4f587a31abe4b91545483d1db9 /techlibs | |
| parent | d4a05b499e58db500c376e3c44e4a1e4c46542c3 (diff) | |
| download | yosys-073e8df9f1ca88ae30f5c61f7a620b02210e1747.tar.gz yosys-073e8df9f1ca88ae30f5c61f7a620b02210e1747.tar.bz2 yosys-073e8df9f1ca88ae30f5c61f7a620b02210e1747.zip | |
greenpak4: replaced MOSI/MISO with single one-way SDAT pin
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/greenpak4/cells_sim.v | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index b3060b14a..3263c4ebc 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -591,7 +591,7 @@ endmodule module GP_SPI( input SCK, - input MOSI, + inout SDAT, input CSN, output reg MISO, input[7:0] TXD_HIGH, @@ -599,7 +599,6 @@ module GP_SPI( output reg[7:0] RXD_HIGH, output reg[7:0] RXD_LOW); - initial MISO = 0; initial DOUT_HIGH = 0; initial DOUT_LOW = 0; |