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| author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-12-20 10:30:38 +0800 |
|---|---|---|
| committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-12-20 10:30:38 +0800 |
| commit | d4a05b499e58db500c376e3c44e4a1e4c46542c3 (patch) | |
| tree | b3fae9a6dd93815d0ad3b4c76b7df8a200068588 /techlibs | |
| parent | eb80ec84aaa8789d554a1246e8d07c33d2882974 (diff) | |
| download | yosys-d4a05b499e58db500c376e3c44e4a1e4c46542c3.tar.gz yosys-d4a05b499e58db500c376e3c44e4a1e4c46542c3.tar.bz2 yosys-d4a05b499e58db500c376e3c44e4a1e4c46542c3.zip | |
greenpak4: Changed port names on GP_SPI for clarity
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/greenpak4/cells_sim.v | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index 6b8280eb2..b3060b14a 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -594,10 +594,10 @@ module GP_SPI( input MOSI, input CSN, output reg MISO, - input[7:0] DIN_HIGH, - input[7:0] DIN_LOW, - output reg[7:0] DOUT_HIGH, - output reg[7:0] DOUT_LOW); + input[7:0] TXD_HIGH, + input[7:0] TXD_LOW, + output reg[7:0] RXD_HIGH, + output reg[7:0] RXD_LOW); initial MISO = 0; initial DOUT_HIGH = 0; |