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| author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-12-15 07:15:38 +0800 |
|---|---|---|
| committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-12-15 07:15:38 +0800 |
| commit | 58da621ac3892bda42e31faa6ac4f02bc9cf3f87 (patch) | |
| tree | 69bb79c7579d4c3da916c332121026c7a1cf83fe /techlibs | |
| parent | 262f8f913cd7b72fa86b0465590c8f6ad9e2d036 (diff) | |
| download | yosys-58da621ac3892bda42e31faa6ac4f02bc9cf3f87.tar.gz yosys-58da621ac3892bda42e31faa6ac4f02bc9cf3f87.tar.bz2 yosys-58da621ac3892bda42e31faa6ac4f02bc9cf3f87.zip | |
greenpak4: Fixed typo
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/greenpak4/cells_sim.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index 83727e9b2..d5a06a453 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -132,7 +132,7 @@ module GP_DAC(input[7:0] DIN, input wire VREF, output reg VOUT); endmodule -module GP_DCMPREF(output OUT) +module GP_DCMPREF(output OUT); parameter[7:0] REF_VAL = 8'h00; wire[7:0] OUT = REF_VAL; endmodule |