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* ecp5: Remove TRELLIS_SLICE and add TRELLIS_COMB modelgatecat2023-04-061-160/+30
* Add iopad_external_pin to some basic io primitivesMiodrag Milanovic2023-03-201-0/+1
* Add missing parameters for ecp5Rick Luiken2022-04-251-0/+1
* ecp5: Do not use specify in generate in cells_sim.v.Marcelina Kościelnicka2022-02-211-28/+15
* ecp5: Fix DPR16X4 sim model.Marcelina Kościelnicka2022-02-091-1/+1
* ecp5: TRELLIS_FF bypass path only in async modeEddie Hung2020-05-141-8/+8
* xilinx/ecp5/ice40: add (* abc9_flop *) to bypass-able cellsEddie Hung2020-05-141-3/+26
* ecp5: (* abc9_flop *) gated behind YOSYSEddie Hung2020-05-141-0/+2
* ecp5: add synth_ecp5 -dff to work with -abc9Eddie Hung2020-05-141-0/+21
* ecp5: remove small LUT entriesEddie Hung2020-02-271-24/+6
* ecp5: deprecate abc9_{arrival,required} and *.{lut,box}Eddie Hung2020-02-271-5/+108
* Nitpick cleanup for ecp5Eddie Hung2019-12-271-10/+2
* Rename abc_* names/attributes to more precisely be abc9_*Eddie Hung2019-10-041-6/+6
* Merge remote-tracking branch 'origin/master' into xaig_arrivalEddie Hung2019-09-021-6/+7
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| * Fix TRELLIS_FF simulation modelMiodrag Milanovic2019-08-311-6/+7
* | Merge remote-tracking branch 'origin/master' into xaig_arrivalEddie Hung2019-08-301-53/+6
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| * ecp5: Add simulation equivalence check for Diamond FF implementationsDavid Shah2019-08-301-0/+4
| * ecp5: deduplicate Diamond FD/IFS/OFS/IO primitives.whitequark2019-08-301-55/+2
| * ecp5: add missing FD primitives.whitequark2019-08-301-36/+38
| * ecp5: fix CEMUX on IFS/OFS primitives.whitequark2019-08-301-9/+9
* | Fix spacingEddie Hung2019-08-231-1/+1
* | Merge remote-tracking branch 'origin/master' into xaig_arrivalEddie Hung2019-08-231-3/+6
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| * Put abc_* attributes above portEddie Hung2019-08-231-5/+10
* | ecp5 to use -max_iter 1Eddie Hung2019-08-201-1/+1
* | ecp5 to use abc_map.v and _unmap.vEddie Hung2019-08-201-4/+3
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* Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithroEddie Hung2019-08-191-2/+2
* Update abc_* attr in ecp5 and ice40Eddie Hung2019-08-161-9/+13
* ecp5: Make cells_sim.v consistent with nextpnrDavid Shah2019-08-071-101/+244
* Disable boxing of ECP5 dist RAM due to regressionEddie Hung2019-06-281-1/+1
* Add write address to abc_scc_break of ECP5 dist RAMEddie Hung2019-06-281-1/+1
* Refactor for one "abc_carry" attribute on moduleEddie Hung2019-06-271-5/+3
* Merge origin/masterEddie Hung2019-06-271-41/+53
* Add WE to ECP5 dist RAM's abc_scc_break tooEddie Hung2019-06-261-1/+1
* Re-enable dist RAM boxes for ECP5Eddie Hung2019-06-241-1/+1
* Revert "Re-enable dist RAM boxes for ECP5"Eddie Hung2019-06-241-1/+1
* Re-enable dist RAM boxes for ECP5Eddie Hung2019-06-241-1/+1
* Comment out dist RAM boxing on ECP5 for nowEddie Hung2019-06-141-1/+1
* Remove WIP ABC9 flop supportEddie Hung2019-06-141-3/+3
* ecp5: Add abc9 optionDavid Shah2019-06-141-11/+21
* Fix ECP5 cells_sim for iverilogMiodrag Milanovic2019-03-011-2/+3
* Merge pull request #794 from daveshah1/ecp5improveClifford Wolf2019-02-281-7/+33
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| * ecp5: Compatibility with Migen AsyncResetSynchronizerDavid Shah2019-02-251-0/+17
| * ecp5: Add LSRMODE to flipflops for PRLD supportDavid Shah2019-01-211-7/+16
* | Clean up some whitepsace outliersLarry Doolittle2019-02-261-2/+2
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* ecp5: Adding some blackbox cellsDavid Shah2018-11-071-1/+1
* ecp5: Sim model fixesDavid Shah2018-10-191-3/+5
* ecp5: First BRAM type maps successfullyDavid Shah2018-10-101-0/+2
* ecp5: Script for BRAM IO connectionsDavid Shah2018-10-101-64/+64
* ecp5: Adding BRAM initialisation and configDavid Shah2018-10-091-0/+4
* ecp5: Add blackbox for DP16KDDavid Shah2018-10-051-0/+93
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