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| author | David Shah <davey1576@gmail.com> | 2019-02-19 19:35:10 +0000 |
|---|---|---|
| committer | David Shah <dave@ds0.me> | 2019-02-25 13:24:30 +0000 |
| commit | fa2f595cfa240b86edb26e859449c1c54eaf49ef (patch) | |
| tree | 629e892807c85df0d8d762295ac8bb7db8b04b66 /techlibs/ecp5/cells_sim.v | |
| parent | bb56cb738d6586059855cc3deefad12119673157 (diff) | |
| download | yosys-fa2f595cfa240b86edb26e859449c1c54eaf49ef.tar.gz yosys-fa2f595cfa240b86edb26e859449c1c54eaf49ef.tar.bz2 yosys-fa2f595cfa240b86edb26e859449c1c54eaf49ef.zip | |
ecp5: Compatibility with Migen AsyncResetSynchronizer
Signed-off-by: David Shah <davey1576@gmail.com>
Diffstat (limited to 'techlibs/ecp5/cells_sim.v')
| -rw-r--r-- | techlibs/ecp5/cells_sim.v | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v index ca5d020f3..d2d8b5793 100644 --- a/techlibs/ecp5/cells_sim.v +++ b/techlibs/ecp5/cells_sim.v @@ -556,3 +556,20 @@ module DP16KD( parameter INITVAL_3E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; parameter INITVAL_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; endmodule + +// For Diamond compatibility, FIXME: add all Diamond flipflop mappings +module FD1S3BX(input PD, D, CK, output Q); + TRELLIS_FF #( + .GSR("DISABLED"), + .CEMUX("1"), + .CLKMUX("CLK"), + .LSRMUX("LSR"), + .REGSET("SET"), + .SRMODE("ASYNC") + ) tff_i ( + .CLK(CK), + .LSR(PD), + .DI(D), + .Q(Q) + ); +endmodule |