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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-24 21:55:54 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-24 21:55:54 -0700 |
| commit | ca0225fcfaa8c9c68647034351a1569464959edf (patch) | |
| tree | cf90e1aa4ba34fd59e3830fc01e6ef495f69b103 /techlibs/ecp5/cells_sim.v | |
| parent | 152e682bd5e448aaca20e7c9349c88bbd4a8ed3b (diff) | |
| download | yosys-ca0225fcfaa8c9c68647034351a1569464959edf.tar.gz yosys-ca0225fcfaa8c9c68647034351a1569464959edf.tar.bz2 yosys-ca0225fcfaa8c9c68647034351a1569464959edf.zip | |
Re-enable dist RAM boxes for ECP5
Diffstat (limited to 'techlibs/ecp5/cells_sim.v')
| -rw-r--r-- | techlibs/ecp5/cells_sim.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v index f66147323..567942482 100644 --- a/techlibs/ecp5/cells_sim.v +++ b/techlibs/ecp5/cells_sim.v @@ -106,7 +106,7 @@ module PFUMX (input ALUT, BLUT, C0, output Z); endmodule // --------------------------------------- -//(* abc_box_id=2 *) +(* abc_box_id=2, abc_scc_break="D" *) module TRELLIS_DPR16X4 ( input [3:0] DI, input [3:0] WAD, |