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| author | Larry Doolittle <ldoolitt@recycle.lbl.gov> | 2019-02-24 22:08:52 -0800 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-02-26 09:39:46 -0800 |
| commit | 61fc411c5d7237e420ee6eb9f6eb093e70d1007d (patch) | |
| tree | 52cab3b364be7ac5d98ef467a545ad651c02570b /techlibs/ecp5/cells_sim.v | |
| parent | c258b99040c8414952a3aceae874dc47563540dc (diff) | |
| download | yosys-61fc411c5d7237e420ee6eb9f6eb093e70d1007d.tar.gz yosys-61fc411c5d7237e420ee6eb9f6eb093e70d1007d.tar.bz2 yosys-61fc411c5d7237e420ee6eb9f6eb093e70d1007d.zip | |
Clean up some whitepsace outliers
Diffstat (limited to 'techlibs/ecp5/cells_sim.v')
| -rw-r--r-- | techlibs/ecp5/cells_sim.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v index 507ab1beb..f27540bd7 100644 --- a/techlibs/ecp5/cells_sim.v +++ b/techlibs/ecp5/cells_sim.v @@ -57,7 +57,7 @@ module TRELLIS_RAM16X2 ( input RAD0, RAD1, RAD2, RAD3, output DO0, DO1 ); - parameter WCKMUX = "WCK"; + parameter WCKMUX = "WCK"; parameter WREMUX = "WRE"; parameter INITVAL_0 = 16'h0000; parameter INITVAL_1 = 16'h0000; @@ -104,7 +104,7 @@ module TRELLIS_DPR16X4 ( input [3:0] RAD, output [3:0] DO ); - parameter WCKMUX = "WCK"; + parameter WCKMUX = "WCK"; parameter WREMUX = "WRE"; parameter [63:0] INITVAL = 64'h0000000000000000; |