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| author | Miodrag Milanovic <mmicko@gmail.com> | 2023-03-17 16:45:03 +0100 |
|---|---|---|
| committer | myrtle <gatecat@ds0.me> | 2023-03-20 09:17:22 +0100 |
| commit | db367bd69ee4053f0846c55657b4680d62a1eb27 (patch) | |
| tree | aeb8dce40b80ea76c76ff692dfc0c86cd9fab6f6 /techlibs/ecp5/cells_sim.v | |
| parent | 10589c57bfd0e5dd29c739e9d9db044cdb8ad8ed (diff) | |
| download | yosys-db367bd69ee4053f0846c55657b4680d62a1eb27.tar.gz yosys-db367bd69ee4053f0846c55657b4680d62a1eb27.tar.bz2 yosys-db367bd69ee4053f0846c55657b4680d62a1eb27.zip | |
Add iopad_external_pin to some basic io primitives
Diffstat (limited to 'techlibs/ecp5/cells_sim.v')
| -rw-r--r-- | techlibs/ecp5/cells_sim.v | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v index f9d503deb..95f612cfa 100644 --- a/techlibs/ecp5/cells_sim.v +++ b/techlibs/ecp5/cells_sim.v @@ -378,6 +378,7 @@ endmodule // --------------------------------------- (* keep *) module TRELLIS_IO( + (* iopad_external_pin *) inout B, input I, input T, |