| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | proc_clean: remove any empty cases if all cases use all-def compare. | whitequark | 2018-12-23 | 1 | -0/+10 |
| * | Documentation improvements etc. | Ruben Undheim | 2018-10-13 | 1 | -3/+1 |
| * | Support for 'modports' for System Verilog interfaces | Ruben Undheim | 2018-10-12 | 1 | -1/+1 |
| * | Synthesis support for SystemVerilog interfaces | Ruben Undheim | 2018-10-12 | 1 | -0/+15 |
| * | Add $allconst and $allseq cell types | Clifford Wolf | 2018-02-23 | 1 | -1/+21 |
| * | Bugfix in hierarchy handling of blackbox module ports | Clifford Wolf | 2018-01-05 | 1 | -1/+3 |
| * | Add RTLIL::Const::is_fully_ones() | Clifford Wolf | 2017-12-14 | 1 | -0/+11 |
| * | Add SigSpec::is_fully_ones() | Clifford Wolf | 2017-12-14 | 1 | -0/+15 |
| * | Add src arguments to all cell creator helper functions | Clifford Wolf | 2017-09-09 | 1 | -56/+91 |
| * | Update more stuff to use get_src_attribute() and set_src_attribute() | Clifford Wolf | 2017-09-01 | 1 | -1/+1 |
| * | Merge remote-tracking branch 'upstream/master' | Jason Lowdermilk | 2017-08-30 | 1 | -0/+16 |
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| | * | Add {get,set}_src_attribute() methods on RTLIL::AttrObject | Clifford Wolf | 2017-08-30 | 1 | -0/+16 |
| * | | fix indent level | Jason Lowdermilk | 2017-08-30 | 1 | -2/+2 |
| * | | Add support for source line tracking through synthesis phase | Jason Lowdermilk | 2017-08-29 | 1 | -3/+4 |
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| * | Add Const methods is_fully_zero(), is_fully_def(), and is_fully_undef() | Clifford Wolf | 2017-08-18 | 1 | -0/+33 |
| * | Add $_ANDNOT_ and $_ORNOT_ gates | Clifford Wolf | 2017-05-17 | 1 | -26/+30 |
| * | Add $live and $fair cell types, add support for s_eventually keyword | Clifford Wolf | 2017-02-25 | 1 | -1/+17 |
| * | Add $cover cell type and SVA cover() support | Clifford Wolf | 2017-02-04 | 1 | -1/+9 |
| * | Fix RTLIL::Memory::start_offset initialization | Clifford Wolf | 2017-01-25 | 1 | -0/+1 |
| * | Bugfix in RTLIL::SigSpec::remove2() | Clifford Wolf | 2016-12-31 | 1 | -3/+4 |
| * | Remember global declarations and defines accross read_verilog calls | Clifford Wolf | 2016-11-15 | 1 | -0/+2 |
| * | Added $anyseq cell type | Clifford Wolf | 2016-10-14 | 1 | -1/+10 |
| * | Added $ff and $_FF_ cell types | Clifford Wolf | 2016-10-12 | 1 | -0/+25 |
| * | Improvements in assertpmux | Clifford Wolf | 2016-09-07 | 1 | -0/+16 |
| * | Removed $aconst cell type | Clifford Wolf | 2016-08-30 | 1 | -1/+1 |
| * | Removed $predict again | Clifford Wolf | 2016-08-28 | 1 | -9/+1 |
| * | Fixed handling of transparent bram rd ports on ROMs | Clifford Wolf | 2016-08-27 | 1 | -0/+1 |
| * | Added $anyconst and $aconst | Clifford Wolf | 2016-07-27 | 1 | -0/+6 |
| * | Added $initstate cell type and vlog function | Clifford Wolf | 2016-07-21 | 1 | -0/+6 |
| * | After reading the SV spec, using non-standard predict() instead of expect() | Clifford Wolf | 2016-07-21 | 1 | -2/+2 |
| * | Added basic support for $expect cells | Clifford Wolf | 2016-07-13 | 1 | -8/+17 |
| * | A few modifications after pull request comments | Ruben Undheim | 2016-06-18 | 1 | -1/+1 |
| * | Added support for SystemVerilog packages with localparam definitions | Ruben Undheim | 2016-06-18 | 1 | -0/+2 |
| * | Improved support for $sop cells | Clifford Wolf | 2016-06-17 | 1 | -1/+1 |
| * | Added $sop cell type and "abc -sop" | Clifford Wolf | 2016-06-17 | 1 | -0/+9 |
| * | Added addBufGate module method | Clifford Wolf | 2016-02-02 | 1 | -0/+1 |
| * | rtlil: Improve performance of SigSpec::extract(SigSpec, SigSpec*) | Rick Altherr | 2016-01-31 | 1 | -2/+31 |
| * | rtlil: speed up SigSpec::sort_and_unify() | Rick Altherr | 2016-01-31 | 1 | -1/+11 |
| * | rtlil: improve performance of SigSpec::replace(SigSpec, SigSpec, SigSpec*) | Rick Altherr | 2016-01-31 | 1 | -6/+14 |
| * | rtlil: improve performance of SigSpec::remove2(SigSpec, SigSpec*) | Rick Altherr | 2016-01-31 | 1 | -2/+29 |
| * | rtlil: rewrite remove2() to avoid copying | Rick Altherr | 2016-01-30 | 1 | -45/+18 |
| * | rtlil: duplicate remove2() for std::set<> | Rick Altherr | 2016-01-29 | 1 | -0/+39 |
| * | Import more std:: stuff into Yosys namespace | Clifford Wolf | 2015-10-25 | 1 | -14/+14 |
| * | renamed SigSpec::to_single_sigbit() to SigSpec::as_bit(), added is_bit() | Clifford Wolf | 2015-10-24 | 1 | -12/+11 |
| * | Fixed driver conflict handling (various cmds) | Clifford Wolf | 2015-10-24 | 1 | -3/+12 |
| * | Fixed handling of driver-driver conflicts in wreduce | Clifford Wolf | 2015-10-24 | 1 | -0/+4 |
| * | Added read-enable to memory model | Clifford Wolf | 2015-09-25 | 1 | -0/+2 |
| * | Cosmetic fix in Module::addLut() | Clifford Wolf | 2015-09-18 | 1 | -4/+4 |
| * | Added $tribuf and $_TBUF_ cell types | Clifford Wolf | 2015-08-16 | 1 | -0/+20 |
| * | Fixed handling of [a-fxz?] in decimal constants | Clifford Wolf | 2015-08-11 | 1 | -0/+4 |
