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| author | Jason Lowdermilk <jlowder@chipscan.us> | 2017-08-30 11:46:41 -0600 |
|---|---|---|
| committer | Jason Lowdermilk <jlowder@chipscan.us> | 2017-08-30 11:46:41 -0600 |
| commit | 271e8ba7cdc223ba8ee745ac1a5c837235398c54 (patch) | |
| tree | 8bd9b45b6645a7871d678c0560bc87a2d82d736e /kernel/rtlil.cc | |
| parent | 32c0f1193e3fffdfed2fc99d48f05772661a4051 (diff) | |
| download | yosys-271e8ba7cdc223ba8ee745ac1a5c837235398c54.tar.gz yosys-271e8ba7cdc223ba8ee745ac1a5c837235398c54.tar.bz2 yosys-271e8ba7cdc223ba8ee745ac1a5c837235398c54.zip | |
fix indent level
Diffstat (limited to 'kernel/rtlil.cc')
| -rw-r--r-- | kernel/rtlil.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index f132d299b..9a97faf45 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1620,7 +1620,7 @@ RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *oth } #define DEF_METHOD(_func, _y_size, _type) \ - RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed, std::string src) { \ + RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed, std::string src) { \ RTLIL::Cell *cell = addCell(name, _type); \ cell->parameters["\\A_SIGNED"] = is_signed; \ cell->parameters["\\A_WIDTH"] = sig_a.size(); \ @@ -1630,7 +1630,7 @@ RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *oth if (!src.empty()) cell->attributes["\\src"] = src; \ return cell; \ } \ - RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed, std::string src) { \ + RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed, std::string src) { \ RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \ add ## _func(name, sig_a, sig_y, is_signed, src); \ return sig_y; \ |