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| author | Clifford Wolf <clifford@clifford.at> | 2017-12-14 02:06:39 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-12-14 02:06:39 +0100 |
| commit | 76afff7ef67265b296455649c9bc6f0196aa5390 (patch) | |
| tree | 188c184f997e7b6450f6dbc3ab82a7d6ccc6af54 /kernel/rtlil.cc | |
| parent | 96ad6888496f4cd34bbf461ce26f97f598bf898c (diff) | |
| download | yosys-76afff7ef67265b296455649c9bc6f0196aa5390.tar.gz yosys-76afff7ef67265b296455649c9bc6f0196aa5390.tar.bz2 yosys-76afff7ef67265b296455649c9bc6f0196aa5390.zip | |
Add RTLIL::Const::is_fully_ones()
Diffstat (limited to 'kernel/rtlil.cc')
| -rw-r--r-- | kernel/rtlil.cc | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 7dc7107c1..3e873054f 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -172,6 +172,17 @@ bool RTLIL::Const::is_fully_zero() const return true; } +bool RTLIL::Const::is_fully_ones() const +{ + cover("kernel.rtlil.const.is_fully_ones"); + + for (auto bit : bits) + if (bit != RTLIL::State::S1) + return false; + + return true; +} + bool RTLIL::Const::is_fully_def() const { cover("kernel.rtlil.const.is_fully_def"); |