aboutsummaryrefslogtreecommitdiffstats
path: root/kernel/rtlil.cc
Commit message (Expand)AuthorAgeFilesLines
* backends/rtlil: Do not shorten a value with z bits to 'xJannis Harder2023-01-291-0/+11
* Add bitwise `$bweqx` and `$bwmux` cellsJannis Harder2022-11-301-0/+36
* Add the $anyinit cell and the formalff passJannis Harder2022-08-161-0/+17
* Assorted microoptimization speedups in core data structures.Marcelina Kościelnicka2022-07-271-120/+61
* Add a check for packed memory MEMID uniquenessMarcelina Kościelnicka2022-06-131-0/+10
* Use compiler-generated default constructor for RTLIL::Const::ConstHenner Zeller2022-06-091-9/+1
* Add some more reserve calls to RTLIL::ConstNotAFile2022-03-251-0/+5
* Add $bmux and $demux cells.Marcelina Kościelnicka2022-01-281-2/+45
* sta: very crude static timing analysis passLofty2021-11-251-0/+29
* verilog: use derived module info to elaborate cell connectionsZachary Snow2021-10-251-0/+5
* Split out logic for reprocessing an AstModuleRupert Swarbrick2021-10-251-2/+2
* Add $aldff and $aldffe: flip-flops with async load.Marcelina Kościelnicka2021-10-021-0/+110
* Add additional check to SigSpecClaire Xenia Wolf2021-09-101-4/+12
* Generate an RTLIL representation of bind constructsRupert Swarbrick2021-08-131-0/+17
* Add v2 memory cells.Marcelina Kościelnicka2021-08-111-2/+68
* memory: Introduce $meminit_v2 cell, with EN input.Marcelina Kościelnicka2021-07-281-1/+11
* rtlil: Make Process handling more uniform with Cell and Wire.Marcelina Kościelnicka2021-07-121-1/+31
* Simplify some RTLIL destructorsRupert Swarbrick2021-06-141-10/+10
* opt_expr: Fix mul/div/mod by POT patterns to support >= 32 bits.Marcelina Kościelnicka2021-06-091-0/+33
* Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-081-1/+1
* kernel/rtlil: Extract some helpers for checking memory cell types.Marcelina Kościelnicka2021-05-221-0/+10
* rtlil: add const accessors for modules, wires, and cellsZachary Snow2021-03-251-0/+5
* blackbox: Include whiteboxed modulesgatecat2021-03-171-2/+2
* rtlil: Disallow 0-width chunks in SigSpec.Marcelina Kościelnicka2021-03-151-18/+49
* Add support for memory writes in processes.Marcelina Kościelnicka2021-03-081-0/+1
* Replace assert in addModule with more useful error messageDan Ravensloft2021-03-061-1/+2
* bugpoint: add -wires option.whitequark2020-12-071-1/+1
* Replace "ILANG" with "RTLIL" everywhere.whitequark2020-08-261-2/+2
* Ensure \A_SIGNED is never used with $shiftxXiretza2020-08-181-1/+5
* Add add* functions for the new FF typesMarcelina Kościelnicka2020-06-231-0/+193
* Add new builtin FF typesMarcelina Kościelnicka2020-06-231-47/+224
* RTLIL: add Module::addProcess, use it in Module::cloneInto. NFC.whitequark2020-06-091-2/+10
* flatten: preserve original object names via hdlname attribute.whitequark2020-06-081-0/+16
* RTLIL: use {get,set}_string_attribute in {get,set}_strpool_attribute.whitequark2020-06-081-2/+2
* Merge pull request #2105 from whitequark/split-flatten-off-techmapclairexen2020-06-081-0/+12
|\
| * RTLIL: factor out RTLIL::Module::addMemory. NFC.whitequark2020-06-041-0/+12
* | Merge pull request #2006 from jersey99/signed-in-rtlil-wirewhitequark2020-06-041-0/+2
|\ \ | |/ |/|
| * Preserve 'signed'-ness of a verilog wire through RTLILVamsi K Vytla2020-04-271-0/+2
* | Add flooring division operatorXiretza2020-05-281-1/+2
* | Add flooring modulo operatorXiretza2020-05-281-1/+2
|/
* kernel: Cell::getParam() to throw exception again if not foundEddie Hung2020-04-221-3/+2
* Use default parameter value in getParamMarcelina Kościelnicka2020-04-211-1/+10
* ilang, ast: Store parameter order and default value information.Marcelina Kościelnicka2020-04-211-1/+2
* rtlil: add AttrObject::has_attribute.whitequark2020-04-161-0/+5
* rtlil: add AttrObject::{get,set}_string_attribute.whitequark2020-04-161-17/+17
* Merge pull request #1927 from YosysHQ/eddie/design_remove_assertEddie Hung2020-04-161-0/+1
|\
| * kernel: Design::remove(RTLIL::Module *) to check refcount_modules_Eddie Hung2020-04-141-0/+1
* | kernel: Module::makeblackbox() to clear connections tooEddie Hung2020-04-131-0/+2
|/
* Merge pull request #1858 from YosysHQ/eddie/fix1856Eddie Hung2020-04-091-1/+1
|\
| * kernel: include "kernel/constids.inc" instead of "constids.inc"Eddie Hung2020-04-091-1/+1
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-09 15:30:15 +0000