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| author | Clifford Wolf <clifford@clifford.at> | 2017-12-12 21:48:31 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-12-14 01:29:09 +0100 |
| commit | 96ad6888496f4cd34bbf461ce26f97f598bf898c (patch) | |
| tree | fa7d096bef320378f26e22177c4781cb00de156d /kernel/rtlil.cc | |
| parent | 1dad2ff6828696536aa1bfade099996b350ffeb6 (diff) | |
| download | yosys-96ad6888496f4cd34bbf461ce26f97f598bf898c.tar.gz yosys-96ad6888496f4cd34bbf461ce26f97f598bf898c.tar.bz2 yosys-96ad6888496f4cd34bbf461ce26f97f598bf898c.zip | |
Add SigSpec::is_fully_ones()
Diffstat (limited to 'kernel/rtlil.cc')
| -rw-r--r-- | kernel/rtlil.cc | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 8c3d2962c..7dc7107c1 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -3353,6 +3353,21 @@ bool RTLIL::SigSpec::is_fully_zero() const return true; } +bool RTLIL::SigSpec::is_fully_ones() const +{ + cover("kernel.rtlil.sigspec.is_fully_ones"); + + pack(); + for (auto it = chunks_.begin(); it != chunks_.end(); it++) { + if (it->width > 0 && it->wire != NULL) + return false; + for (size_t i = 0; i < it->data.size(); i++) + if (it->data[i] != RTLIL::State::S1) + return false; + } + return true; +} + bool RTLIL::SigSpec::is_fully_def() const { cover("kernel.rtlil.sigspec.is_fully_def"); |