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authorClifford Wolf <clifford@clifford.at>2017-02-25 10:36:39 +0100
committerClifford Wolf <clifford@clifford.at>2017-02-25 10:36:39 +0100
commit5f1d0b1024981b6ede2988bf8c5812b37c87d0e9 (patch)
tree75e48829241c9c65b5c9c7a34cc21048285ea48b /kernel/rtlil.cc
parent7af9727f78263d2fc41178396791f51a680acdfa (diff)
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Add $live and $fair cell types, add support for s_eventually keyword
Diffstat (limited to 'kernel/rtlil.cc')
-rw-r--r--kernel/rtlil.cc18
1 files changed, 17 insertions, 1 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 978a7a537..6ce3f1376 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -1026,7 +1026,7 @@ namespace {
return;
}
- if (cell->type.in("$assert", "$assume", "$cover")) {
+ if (cell->type.in("$assert", "$assume", "$live", "$fair", "$cover")) {
port("\\A", 1);
port("\\EN", 1);
check_expected();
@@ -1819,6 +1819,22 @@ RTLIL::Cell* RTLIL::Module::addAssume(RTLIL::IdString name, RTLIL::SigSpec sig_a
return cell;
}
+RTLIL::Cell* RTLIL::Module::addLive(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en)
+{
+ RTLIL::Cell *cell = addCell(name, "$live");
+ cell->setPort("\\A", sig_a);
+ cell->setPort("\\EN", sig_en);
+ return cell;
+}
+
+RTLIL::Cell* RTLIL::Module::addFair(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en)
+{
+ RTLIL::Cell *cell = addCell(name, "$fair");
+ cell->setPort("\\A", sig_a);
+ cell->setPort("\\EN", sig_en);
+ return cell;
+}
+
RTLIL::Cell* RTLIL::Module::addCover(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en)
{
RTLIL::Cell *cell = addCell(name, "$cover");