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| author | Clifford Wolf <clifford@clifford.at> | 2016-06-17 16:31:16 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-06-17 16:31:16 +0200 |
| commit | 95757efb25dc51a73b384b475b0fc87d0e11d10e (patch) | |
| tree | b0c4518d676e8389629ca96482231616232add14 /kernel/rtlil.cc | |
| parent | 52bb1b968d4bfbbbd84eca88f0e80c486cc1a16e (diff) | |
| download | yosys-95757efb25dc51a73b384b475b0fc87d0e11d10e.tar.gz yosys-95757efb25dc51a73b384b475b0fc87d0e11d10e.tar.bz2 yosys-95757efb25dc51a73b384b475b0fc87d0e11d10e.zip | |
Improved support for $sop cells
Diffstat (limited to 'kernel/rtlil.cc')
| -rw-r--r-- | kernel/rtlil.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 3b1df4406..bcd87d3ff 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -2142,7 +2142,7 @@ void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed) return; } - if (type == "$lut") { + if (type == "$lut" || type == "$sop") { parameters["\\WIDTH"] = GetSize(connections_["\\A"]); return; } |