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| author | Ruben Undheim <ruben.undheim@gmail.com> | 2016-06-18 10:24:21 +0200 |
|---|---|---|
| committer | Ruben Undheim <ruben.undheim@gmail.com> | 2016-06-18 10:53:55 +0200 |
| commit | 178ff3e7f6f9766f0b1a3e8dcc96e030aea59b15 (patch) | |
| tree | 0da57cc51ffbe1f20d7ca326753b1ab8c5585769 /kernel/rtlil.cc | |
| parent | 3380281e15ca61cec8beda70938fb7b6f4c121d6 (diff) | |
| download | yosys-178ff3e7f6f9766f0b1a3e8dcc96e030aea59b15.tar.gz yosys-178ff3e7f6f9766f0b1a3e8dcc96e030aea59b15.tar.bz2 yosys-178ff3e7f6f9766f0b1a3e8dcc96e030aea59b15.zip | |
Added support for SystemVerilog packages with localparam definitions
Diffstat (limited to 'kernel/rtlil.cc')
| -rw-r--r-- | kernel/rtlil.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index bcd87d3ff..9e09d9f04 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -304,6 +304,8 @@ RTLIL::Design::~Design() { for (auto it = modules_.begin(); it != modules_.end(); ++it) delete it->second; + for (auto n : packages) + delete n; } RTLIL::ObjRange<RTLIL::Module*> RTLIL::Design::modules() |