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authorClifford Wolf <clifford@clifford.at>2016-09-07 12:42:16 +0200
committerClifford Wolf <clifford@clifford.at>2016-09-07 12:42:16 +0200
commitcb7dbf4070a7ca3658b7e473cb54f2eafb6c9ae3 (patch)
tree1042f049c96c5c9cd587d70a6cea85d4310d8cb3 /kernel/rtlil.cc
parente2570ffb872382f190b98d89b2eb7995a5d46758 (diff)
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Improvements in assertpmux
Diffstat (limited to 'kernel/rtlil.cc')
-rw-r--r--kernel/rtlil.cc16
1 files changed, 16 insertions, 0 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 41b4b93f0..32efe4f0d 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -1975,6 +1975,22 @@ RTLIL::Cell* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name, RTLIL::SigSpec
return cell;
}
+RTLIL::SigSpec RTLIL::Module::Anyconst(RTLIL::IdString name, int width)
+{
+ RTLIL::SigSpec sig = addWire(NEW_ID, width);
+ Cell *cell = addCell(name, "$anyconst");
+ cell->setParam("\\WIDTH", width);
+ cell->setPort("\\Y", sig);
+ return sig;
+}
+
+RTLIL::SigSpec RTLIL::Module::Initstate(RTLIL::IdString name)
+{
+ RTLIL::SigSpec sig = addWire(NEW_ID);
+ Cell *cell = addCell(name, "$initstate");
+ cell->setPort("\\Y", sig);
+ return sig;
+}
RTLIL::Wire::Wire()
{