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| author | Jason Lowdermilk <jlowder@chipscan.us> | 2017-08-29 14:46:35 -0600 |
|---|---|---|
| committer | Jason Lowdermilk <jlowder@chipscan.us> | 2017-08-29 14:46:35 -0600 |
| commit | 32c0f1193e3fffdfed2fc99d48f05772661a4051 (patch) | |
| tree | 31d7b366715ea199146cd6910bae84a3215d8b74 /kernel/rtlil.cc | |
| parent | 393b18e8e17432349797a1f228a7ddc7e2f7a16c (diff) | |
| download | yosys-32c0f1193e3fffdfed2fc99d48f05772661a4051.tar.gz yosys-32c0f1193e3fffdfed2fc99d48f05772661a4051.tar.bz2 yosys-32c0f1193e3fffdfed2fc99d48f05772661a4051.zip | |
Add support for source line tracking through synthesis phase
Diffstat (limited to 'kernel/rtlil.cc')
| -rw-r--r-- | kernel/rtlil.cc | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 4427303cc..f132d299b 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1620,18 +1620,19 @@ RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *oth } #define DEF_METHOD(_func, _y_size, _type) \ - RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed) { \ + RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed, std::string src) { \ RTLIL::Cell *cell = addCell(name, _type); \ cell->parameters["\\A_SIGNED"] = is_signed; \ cell->parameters["\\A_WIDTH"] = sig_a.size(); \ cell->parameters["\\Y_WIDTH"] = sig_y.size(); \ cell->setPort("\\A", sig_a); \ cell->setPort("\\Y", sig_y); \ + if (!src.empty()) cell->attributes["\\src"] = src; \ return cell; \ } \ - RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed) { \ + RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed, std::string src) { \ RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \ - add ## _func(name, sig_a, sig_y, is_signed); \ + add ## _func(name, sig_a, sig_y, is_signed, src); \ return sig_y; \ } DEF_METHOD(Not, sig_a.size(), "$not") |