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author | Clifford Wolf <clifford@clifford.at> | 2016-08-28 21:35:33 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2016-08-28 21:35:33 +0200 |
commit | eae390ae17839bf0273b32149f46a2560a23d934 (patch) | |
tree | 218b3327ef63938a762859386f23215cef83c4d3 /kernel/rtlil.cc | |
parent | 66582964bc11aadf3d0783a346706d801451a13f (diff) | |
download | yosys-eae390ae17839bf0273b32149f46a2560a23d934.tar.gz yosys-eae390ae17839bf0273b32149f46a2560a23d934.tar.bz2 yosys-eae390ae17839bf0273b32149f46a2560a23d934.zip |
Removed $predict again
Diffstat (limited to 'kernel/rtlil.cc')
-rw-r--r-- | kernel/rtlil.cc | 10 |
1 files changed, 1 insertions, 9 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 72809d42d..de492bcc6 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1017,7 +1017,7 @@ namespace { return; } - if (cell->type.in("$assert", "$assume", "$predict")) { + if (cell->type.in("$assert", "$assume")) { port("\\A", 1); port("\\EN", 1); check_expected(); @@ -1809,14 +1809,6 @@ RTLIL::Cell* RTLIL::Module::addAssume(RTLIL::IdString name, RTLIL::SigSpec sig_a return cell; } -RTLIL::Cell* RTLIL::Module::addExpect(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en) -{ - RTLIL::Cell *cell = addCell(name, "$predict"); - cell->setPort("\\A", sig_a); - cell->setPort("\\EN", sig_en); - return cell; -} - RTLIL::Cell* RTLIL::Module::addEquiv(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y) { RTLIL::Cell *cell = addCell(name, "$equiv"); |